323 lines
9.0 KiB
Plaintext
323 lines
9.0 KiB
Plaintext
--- Test 1: net driver/load queries ---
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net n1 found
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n1 driver pins: 1
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n1 load pins: 1
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net n6 found
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n6 total pins: 4
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Net n1
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Pin capacitance: 1.55-1.70
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Wire capacitance: 0.00
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Total capacitance: 1.55-1.70
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Number of drivers: 1
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Number of loads: 1
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Number of pins: 2
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Driver pins
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buf1/Z output (BUF_X1)
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Load pins
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inv1/A input (INV_X1) 1.55-1.70
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Net n6
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Pin capacitance: 3.82-4.29
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Wire capacitance: 0.00
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Total capacitance: 3.82-4.29
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Number of drivers: 1
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Number of loads: 3
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Number of pins: 4
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Driver pins
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or1/ZN output (OR2_X1)
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Load pins
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buf_out/A input (BUF_X1) 0.88-0.97
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nand1/A1 input (NAND2_X1) 1.53-1.60
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nor1/A1 input (NOR2_X1) 1.41-1.71
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Net n1
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Pin capacitance: 1.55-1.70
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Wire capacitance: 0.00
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Total capacitance: 1.55-1.70
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Number of drivers: 1
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Number of loads: 1
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Number of pins: 2
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Driver pins
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buf1/Z output (BUF_X1)
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Load pins
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inv1/A input (INV_X1) 1.55-1.70
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report_net n1: done
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Net n2
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Pin capacitance: 1.59-1.78
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Wire capacitance: 0.00
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Total capacitance: 1.59-1.78
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Number of drivers: 1
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Number of loads: 1
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Number of pins: 2
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Driver pins
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inv1/ZN output (INV_X1)
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Load pins
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buf2/A input (BUF_X2) 1.59-1.78
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report_net n2: done
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Net n3
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Pin capacitance: 0.79-0.95
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Wire capacitance: 0.00
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Total capacitance: 0.79-0.95
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Number of drivers: 1
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Number of loads: 1
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Number of pins: 2
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Driver pins
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buf2/Z output (BUF_X2)
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Load pins
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or1/A1 input (OR2_X1) 0.79-0.95
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report_net n3: done
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Net n4
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Pin capacitance: 0.87-0.92
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Wire capacitance: 0.00
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Total capacitance: 0.87-0.92
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Number of drivers: 1
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Number of loads: 1
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Number of pins: 2
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Driver pins
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buf3/Z output (BUF_X4)
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Load pins
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and1/A1 input (AND2_X1) 0.87-0.92
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report_net n4: done
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Net n5
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Pin capacitance: 0.90-0.94
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Wire capacitance: 0.00
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Total capacitance: 0.90-0.94
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Number of drivers: 1
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Number of loads: 1
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Number of pins: 2
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Driver pins
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and1/ZN output (AND2_X1)
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Load pins
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or1/A2 input (OR2_X1) 0.90-0.94
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report_net n5: done
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Net n6
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Pin capacitance: 3.82-4.29
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Wire capacitance: 0.00
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Total capacitance: 3.82-4.29
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Number of drivers: 1
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Number of loads: 3
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Number of pins: 4
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Driver pins
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or1/ZN output (OR2_X1)
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Load pins
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buf_out/A input (BUF_X1) 0.88-0.97
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nand1/A1 input (NAND2_X1) 1.53-1.60
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nor1/A1 input (NOR2_X1) 1.41-1.71
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report_net n6: done
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Net n7
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Pin capacitance: 1.06-1.14
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Wire capacitance: 0.00
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Total capacitance: 1.06-1.14
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Number of drivers: 1
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Number of loads: 1
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Number of pins: 2
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Driver pins
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nand1/ZN output (NAND2_X1)
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Load pins
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reg1/D input (DFF_X1) 1.06-1.14
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report_net n7: done
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Net n8
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Pin capacitance: 1.06-1.14
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Wire capacitance: 0.00
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Total capacitance: 1.06-1.14
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Number of drivers: 1
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Number of loads: 1
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Number of pins: 2
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Driver pins
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nor1/ZN output (NOR2_X1)
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Load pins
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reg2/D input (DFF_X1) 1.06-1.14
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report_net n8: done
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--- Test 2: net capacitance queries ---
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n1: total_cap=1.700229965024007e-15 pin_cap=1.700229965024007e-15 wire_cap=0.0
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n2: total_cap=1.7792090110918925e-15 pin_cap=1.7792090110918925e-15 wire_cap=0.0
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n3: total_cap=9.46813957836449e-16 pin_cap=9.46813957836449e-16 wire_cap=0.0
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n4: total_cap=9.181449630663247e-16 pin_cap=9.181449630663247e-16 wire_cap=0.0
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n5: total_cap=9.419389655876452e-16 pin_cap=9.419389655876452e-16 wire_cap=0.0
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n6: total_cap=4.288162317231782e-15 pin_cap=4.288162317231782e-15 wire_cap=0.0
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n7: total_cap=1.140290047274724e-15 pin_cap=1.140290047274724e-15 wire_cap=0.0
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n8: total_cap=1.140290047274724e-15 pin_cap=1.140290047274724e-15 wire_cap=0.0
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--- Test 3: pin property queries ---
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in1: driver=1 load=0 leaf=0 top=1
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in2: driver=1 load=0 leaf=0 top=1
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out1: driver=0 load=1 leaf=0 top=1
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out2: driver=0 load=1 leaf=0 top=1
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out3: driver=0 load=1 leaf=0 top=1
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clk: driver=1 load=0 leaf=0 top=1
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buf1/A: driver=0 load=1 leaf=1 top=0 port=A
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buf1/Z: driver=1 load=0 leaf=1 top=0 port=Z
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inv1/A: driver=0 load=1 leaf=1 top=0 port=A
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inv1/ZN: driver=1 load=0 leaf=1 top=0 port=ZN
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and1/A1: driver=0 load=1 leaf=1 top=0 port=A1
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and1/ZN: driver=1 load=0 leaf=1 top=0 port=ZN
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or1/A1: driver=0 load=1 leaf=1 top=0 port=A1
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or1/ZN: driver=1 load=0 leaf=1 top=0 port=ZN
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reg1/D: driver=0 load=1 leaf=1 top=0 port=D
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reg1/CK: driver=0 load=1 leaf=1 top=0 port=CK
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reg1/Q: driver=1 load=0 leaf=1 top=0 port=Q
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--- Test 4: connected pin queries ---
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buf1/Z connected pins: 2
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inv1/A connected pins: 2
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or1/ZN connected pins: 4
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--- Test 5: instance iterators ---
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top child count: 11
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reg1 pin count: 8
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top net count: 17
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--- Test 6: network counts ---
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instance count: 12
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pin count: 65
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net count: 17
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leaf instance count: 11
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leaf pin count: 56
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--- Test 7: leaf instance iterator ---
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leaf instance count via iterator: 11
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leaf instances list: 11
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--- Test 8: library queries ---
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library: NangateOpenCellLibrary
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library: verilog
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total libraries: 2
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found library: NangateOpenCellLibrary
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found INV_X1 in NangateOpenCellLibrary
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BUF* cells in library: 6
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all cells in library: 134
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--- Test 9: timing reports ---
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Startpoint: in2 (input port clocked by clk)
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Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 v input external delay
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0.00 0.00 v in2 (in)
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0.05 0.05 v buf3/Z (BUF_X4)
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0.03 0.08 v and1/ZN (AND2_X1)
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0.05 0.13 v or1/ZN (OR2_X1)
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0.02 0.15 ^ nor1/ZN (NOR2_X1)
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0.00 0.15 ^ reg2/D (DFF_X1)
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0.15 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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10.00 ^ reg2/CK (DFF_X1)
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-0.04 9.96 library setup time
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9.96 data required time
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---------------------------------------------------------
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9.96 data required time
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-0.15 data arrival time
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---------------------------------------------------------
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9.81 slack (MET)
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Startpoint: in4 (input port clocked by clk)
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Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: min
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 ^ input external delay
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0.00 0.00 ^ in4 (in)
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0.01 0.01 v nor1/ZN (NOR2_X1)
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0.00 0.01 v reg2/D (DFF_X1)
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0.01 data arrival time
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 clock reconvergence pessimism
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0.00 ^ reg2/CK (DFF_X1)
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0.00 0.00 library hold time
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0.00 data required time
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---------------------------------------------------------
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0.00 data required time
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-0.01 data arrival time
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---------------------------------------------------------
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0.01 slack (MET)
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Startpoint: in2 (input port clocked by clk)
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Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: max
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Fanout Cap Slew Delay Time Description
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-----------------------------------------------------------------------------
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0.00 0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 v input external delay
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1 3.00 0.10 0.00 0.00 v in2 (in)
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0.10 0.00 0.00 v buf3/A (BUF_X4)
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1 0.87 0.01 0.05 0.05 v buf3/Z (BUF_X4)
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0.01 0.00 0.05 v and1/A1 (AND2_X1)
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1 0.90 0.01 0.03 0.08 v and1/ZN (AND2_X1)
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0.01 0.00 0.08 v or1/A2 (OR2_X1)
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3 3.82 0.01 0.05 0.13 v or1/ZN (OR2_X1)
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0.01 0.00 0.13 v nor1/A1 (NOR2_X1)
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1 1.14 0.02 0.02 0.15 ^ nor1/ZN (NOR2_X1)
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0.02 0.00 0.15 ^ reg2/D (DFF_X1)
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0.15 data arrival time
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0.00 10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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10.00 ^ reg2/CK (DFF_X1)
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-0.04 9.96 library setup time
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9.96 data required time
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-----------------------------------------------------------------------------
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9.96 data required time
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-0.15 data arrival time
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-----------------------------------------------------------------------------
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9.81 slack (MET)
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Group Slack
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--------------------------------------------
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clk 0.01
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clk 9.81
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max slew
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Pin Limit Slew Slack
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------------------------------------------------------------
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nor1/ZN 0.20 0.02 0.18 (MET)
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max capacitance
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Pin Limit Cap Slack
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------------------------------------------------------------
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nor1/ZN 26.70 1.14 25.56 (MET)
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