216 lines
7.2 KiB
Tcl
216 lines
7.2 KiB
Tcl
# Test multi-library network operations, liberty cell finding across
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# libraries, and various network utility functions.
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# Targets:
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# ConcreteNetwork.cc: findAnyCell, findCellsMatching, findLibCellsMatching,
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# makeInstance(LibertyCell,...), libertyCell queries,
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# addLibrary, findLibrary, deleteLibrary, libertyLibraryIterator,
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# setAttribute, getAttribute, attributeMap, filename, setName
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# Network.cc: findLibertyCell (searches across libs),
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# findLibertyFilename, defaultLibertyLibrary, libertyLibrary(Cell*),
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# libertyLibrary(Instance*), libertyPort, libertyCell(Instance*)
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# SdcNetwork.cc: various port/pin/net find operations
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# ParseBus.cc: parseBusName with non-bus names
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read_liberty ../../test/nangate45/Nangate45_typ.lib
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read_liberty ../../test/nangate45/Nangate45_fast.lib
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read_liberty ../../test/sky130hd/sky130hd_tt.lib
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read_liberty ../../test/ihp-sg13g2/sg13g2_stdcell_typ_1p20V_25C.lib
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#---------------------------------------------------------------
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# Library queries
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# Exercises: library iteration, findLibrary, findLiberty
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#---------------------------------------------------------------
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puts "--- library queries ---"
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set libs [get_libs *]
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puts "total libraries: [llength $libs]"
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# Find specific libraries
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set ng_lib [sta::find_liberty NangateOpenCellLibrary]
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if { $ng_lib != "NULL" } {
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puts " name: [$ng_lib name]"
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}
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set ng_fast [sta::find_liberty NangateOpenCellLibrary_fast]
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set sky_lib [sta::find_liberty sky130_fd_sc_hd__tt_025C_1v80]
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set ihp_lib [sta::find_liberty sg13g2_stdcell_typ_1p20V_25C]
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# Liberty library iterator
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set lib_iter [sta::liberty_library_iterator]
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# Liberty supply exists across libraries
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set vdd_exists [sta::liberty_supply_exists VDD]
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puts "VDD supply exists: $vdd_exists"
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set vss_exists [sta::liberty_supply_exists VSS]
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puts "VSS supply exists: $vss_exists"
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set gnd_exists [sta::liberty_supply_exists GND]
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puts "GND supply exists: $gnd_exists"
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set nope [sta::liberty_supply_exists NONEXISTENT]
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puts "NONEXISTENT: $nope"
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#---------------------------------------------------------------
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# Find liberty cells across multiple libraries
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# Exercises: findLibertyCell (iterates through all libs)
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#---------------------------------------------------------------
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puts "--- cross-library cell queries ---"
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set inv1 [sta::find_liberty_cell INV_X1]
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if { $inv1 != "NULL" } {
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set lib [$inv1 liberty_library]
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puts " from library: [$lib name]"
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}
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# Sky130 cell lookup
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set sky_inv [sta::find_liberty_cell sky130_fd_sc_hd__inv_1]
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if { $sky_inv != "NULL" } {
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set lib [$sky_inv liberty_library]
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puts " from library: [$lib name]"
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}
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# IHP cell lookup
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set ihp_inv [sta::find_liberty_cell sg13g2_inv_1]
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if { $ihp_inv != "NULL" } {
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set lib [$ihp_inv liberty_library]
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puts " from library: [$lib name]"
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}
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#---------------------------------------------------------------
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# Cell pattern matching across libraries
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# Exercises: find_liberty_cells_matching
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#---------------------------------------------------------------
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puts "--- cell pattern matching ---"
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set ng_inv [$ng_lib find_liberty_cells_matching "INV*" 0 0]
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puts "Nangate INV*: [llength $ng_inv]"
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set ng_buf [$ng_lib find_liberty_cells_matching "BUF*" 0 0]
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puts "Nangate BUF*: [llength $ng_buf]"
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set ng_dff [$ng_lib find_liberty_cells_matching "DFF*" 0 0]
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puts "Nangate DFF*: [llength $ng_dff]"
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set ng_sdff [$ng_lib find_liberty_cells_matching "SDFF*" 0 0]
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puts "Nangate SDFF*: [llength $ng_sdff]"
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set ng_all [$ng_lib find_liberty_cells_matching "*" 0 0]
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puts "Nangate all: [llength $ng_all]"
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set sky_inv [$sky_lib find_liberty_cells_matching "*inv*" 0 0]
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puts "Sky130 *inv*: [llength $sky_inv]"
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set sky_buf [$sky_lib find_liberty_cells_matching "*buf*" 0 0]
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puts "Sky130 *buf*: [llength $sky_buf]"
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set sky_dff [$sky_lib find_liberty_cells_matching "*dfxtp*" 0 0]
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puts "Sky130 *dfxtp*: [llength $sky_dff]"
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set sky_latch [$sky_lib find_liberty_cells_matching "*dlx*" 0 0]
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puts "Sky130 *dlx*: [llength $sky_latch]"
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set sky_all [$sky_lib find_liberty_cells_matching "*" 0 0]
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puts "Sky130 all: [llength $sky_all]"
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set ihp_all [$ihp_lib find_liberty_cells_matching "*" 0 0]
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puts "IHP all: [llength $ihp_all]"
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#---------------------------------------------------------------
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# Cell port queries
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# Exercises: find_liberty_port, find_liberty_ports_matching
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#---------------------------------------------------------------
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puts "--- cell port queries ---"
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# Nangate
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set inv_cell [sta::find_liberty_cell INV_X1]
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set inv_a [$inv_cell find_liberty_port A]
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set inv_zn [$inv_cell find_liberty_port ZN]
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set inv_pm [$inv_cell find_liberty_ports_matching "*" 0 0]
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puts "INV_X1 port match *: [llength $inv_pm]"
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set dff_cell [sta::find_liberty_cell DFF_X1]
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set dff_d [$dff_cell find_liberty_port D]
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set dff_ck [$dff_cell find_liberty_port CK]
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set dff_q [$dff_cell find_liberty_port Q]
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set dff_qn [$dff_cell find_liberty_port QN]
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set dff_pm [$dff_cell find_liberty_ports_matching "*" 0 0]
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puts "DFF_X1 port match *: [llength $dff_pm]"
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# SDFF has scan ports
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set sdff_cell [sta::find_liberty_cell SDFF_X1]
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set sdff_pm [$sdff_cell find_liberty_ports_matching "*" 0 0]
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puts "SDFF_X1 port match *: [llength $sdff_pm]"
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set sdff_se [$sdff_cell find_liberty_port SE]
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set sdff_si [$sdff_cell find_liberty_port SI]
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# FA (full adder) - multi-output
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set fa_cell [sta::find_liberty_cell FA_X1]
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set fa_pm [$fa_cell find_liberty_ports_matching "*" 0 0]
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puts "FA_X1 port match *: [llength $fa_pm]"
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# CLKGATETST
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set clkgate_cell [sta::find_liberty_cell CLKGATETST_X1]
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set clkgate_pm [$clkgate_cell find_liberty_ports_matching "*" 0 0]
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puts "CLKGATETST_X1 port match *: [llength $clkgate_pm]"
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# Timing arc sets on cells
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set inv_arcs [$inv_cell timing_arc_sets]
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puts "INV_X1 timing_arc_sets: [llength $inv_arcs]"
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set dff_arcs [$dff_cell timing_arc_sets]
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puts "DFF_X1 timing_arc_sets: [llength $dff_arcs]"
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set sdff_arcs [$sdff_cell timing_arc_sets]
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puts "SDFF_X1 timing_arc_sets: [llength $sdff_arcs]"
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set clkgate_arcs [$clkgate_cell timing_arc_sets]
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puts "CLKGATETST_X1 timing_arc_sets: [llength $clkgate_arcs]"
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#---------------------------------------------------------------
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# Link a design and run timing
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#---------------------------------------------------------------
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read_verilog network_test1.v
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link_design network_test1
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create_clock -name clk -period 10 [get_ports clk]
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set_input_delay -clock clk 0 [get_ports in1]
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set_input_delay -clock clk 0 [get_ports in2]
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set_output_delay -clock clk 0 [get_ports out1]
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set_input_transition 0.1 [all_inputs]
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report_checks
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# Replace with different sizes from same library
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replace_cell buf1 NangateOpenCellLibrary/BUF_X2
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report_checks
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replace_cell buf1 NangateOpenCellLibrary/BUF_X1
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#---------------------------------------------------------------
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# Equiv cells across multiple libraries
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# Exercises: EquivCells with equiv_libs and map_libs
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#---------------------------------------------------------------
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puts "--- equiv cells multi-lib ---"
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set lib1 [lindex [get_libs NangateOpenCellLibrary] 0]
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sta::make_equiv_cells $lib1
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# Find equivs
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set inv_x1 [get_lib_cell NangateOpenCellLibrary/INV_X1]
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set inv_equivs [sta::find_equiv_cells $inv_x1]
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puts "INV_X1 equivs: [llength $inv_equivs]"
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set buf_x1 [get_lib_cell NangateOpenCellLibrary/BUF_X1]
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set buf_equivs [sta::find_equiv_cells $buf_x1]
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puts "BUF_X1 equivs: [llength $buf_equivs]"
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# Find buffers
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set buffers [sta::find_library_buffers $lib1]
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