265 lines
8.7 KiB
Tcl
265 lines
8.7 KiB
Tcl
# Test leaf instance iteration, path name operations, and
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# network count/traversal functions.
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# Targets:
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# Network.cc: leafInstanceIterator, isInside, isHierarchical,
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# pathName (instance, pin, net), pathNameCmp, pathNameLess,
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# portName, isTopInstance, path, findLibertyCell,
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# findLibertyFilename, busIndexInRange, hasMembers,
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# findInstancesMatching, findPinsMatching, findNetsMatching,
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# findPortsMatching (bus and non-bus paths),
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# checkLibertyCorners, checkNetworkLibertyCorners
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# ConcreteNetwork.cc: findAnyCell, deleteLibrary,
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# makeInstance(LibertyCell,...), libertyCell(Cell*),
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# libertyCell(Instance*), cell(LibertyCell*),
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# filename(Cell*), isLeaf(Cell*), setAttribute/getAttribute,
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# netIterator, childIterator, pinIterator, termIterator
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# SdcNetwork.cc: findPort, findPin, findNet with dividers,
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# escapeDividers, escapeBrackets, portDirection
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# ParseBus.cc: parseBusName edge cases
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read_liberty ../../test/nangate45/Nangate45_typ.lib
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read_verilog network_hier_test.v
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link_design network_hier_test
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create_clock -name clk -period 10 [get_ports clk]
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set_input_delay -clock clk 0 [get_ports {in1 in2 in3}]
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set_output_delay -clock clk 0 [get_ports {out1 out2}]
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set_input_transition 0.1 [all_inputs]
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# Build the timing graph
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report_checks
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#---------------------------------------------------------------
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# Leaf instance queries
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# Exercises: leafInstanceIterator, isLeaf, isHierarchical
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#---------------------------------------------------------------
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puts "--- leaf instance queries ---"
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# Get all flat cells (leaf instances)
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set all_flat [get_cells *]
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puts "flat cells: [llength $all_flat]"
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# Get all hierarchical cells
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set all_hier [get_cells -hierarchical *]
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puts "hierarchical cells: [llength $all_hier]"
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# Check specific instances
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foreach inst_name {buf_in sub1 sub2 inv1 reg1 buf_out1 buf_out2} {
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set inst [get_cells $inst_name]
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set ref [get_property $inst ref_name]
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set fn [get_full_name $inst]
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puts "inst $inst_name: ref=$ref full=$fn"
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}
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#---------------------------------------------------------------
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# Test hierarchical instance path traversal
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# Exercises: path, isTopInstance, pathName
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#---------------------------------------------------------------
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puts "--- path traversal ---"
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# Query deep instances through hierarchy
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set deep_cells [get_cells -hierarchical *gate*]
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puts "deep *gate* cells: [llength $deep_cells]"
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# Instance names at various depths
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foreach cell $all_hier {
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set fn [get_full_name $cell]
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set ref [get_property $cell ref_name]
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puts " hier: $fn ref=$ref"
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}
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#---------------------------------------------------------------
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# Test port queries and bus handling
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# Exercises: findPortsMatching, portName, direction
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#---------------------------------------------------------------
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puts "--- port queries ---"
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set all_ports [get_ports *]
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puts "total ports: [llength $all_ports]"
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# Input filter
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set in_ports [get_ports -filter "direction == input"]
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puts "input ports: [llength $in_ports]"
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# Output filter
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set out_ports [get_ports -filter "direction == output"]
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puts "output ports: [llength $out_ports]"
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# Individual port properties
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foreach port_name {clk in1 in2 in3 out1 out2} {
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set p [get_ports $port_name]
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set dir [get_property $p direction]
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set fn [get_full_name $p]
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puts "port $port_name: dir=$dir name=$fn"
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}
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#---------------------------------------------------------------
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# Test pin queries at various levels
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# Exercises: findPinsMatching (flat and hierarchical)
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#---------------------------------------------------------------
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puts "--- pin queries ---"
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set all_pins [get_pins */*]
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puts "flat pins: [llength $all_pins]"
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set hier_pins [get_pins -hierarchical *]
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puts "all hierarchical pins: [llength $hier_pins]"
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# Specific pin patterns
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set a_pins [get_pins */A]
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puts "*/A pins: [llength $a_pins]"
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set z_pins [get_pins */Z]
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puts "*/Z pins: [llength $z_pins]"
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set zn_pins [get_pins */ZN]
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puts "*/ZN pins: [llength $zn_pins]"
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set ck_pins [get_pins */CK]
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puts "*/CK pins: [llength $ck_pins]"
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# Deep hierarchical pin queries
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set sub_pins [get_pins -hierarchical sub*/*]
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puts "sub*/* hier pins: [llength $sub_pins]"
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# All pins within subblocks
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set sub1_pins [get_pins -hierarchical sub1/*]
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puts "sub1/* hier pins: [llength $sub1_pins]"
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set sub2_pins [get_pins -hierarchical sub2/*]
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puts "sub2/* hier pins: [llength $sub2_pins]"
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#---------------------------------------------------------------
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# Test net queries at various levels
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# Exercises: findNetsMatching (flat and hierarchical)
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#---------------------------------------------------------------
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puts "--- net queries ---"
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set all_nets [get_nets *]
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puts "flat nets: [llength $all_nets]"
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set hier_nets [get_nets -hierarchical *]
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puts "hierarchical nets: [llength $hier_nets]"
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# Pattern matching
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set w_nets [get_nets w*]
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puts "w* nets: [llength $w_nets]"
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set hier_w_nets [get_nets -hierarchical w*]
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puts "w* hier nets: [llength $hier_w_nets]"
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# Specific net properties
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foreach net_name {w1 w2 w3 w4 w5} {
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set net [get_nets $net_name]
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set fn [get_full_name $net]
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puts "net $net_name: name=$fn"
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}
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#---------------------------------------------------------------
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# Fanin/fanout traversal through hierarchy
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# Exercises: visitDrvrLoadsThruHierPin, HpinDrvrLoad
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#---------------------------------------------------------------
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puts "--- fanin/fanout traversal ---"
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set fi1 [get_fanin -to [get_ports out1] -flat]
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puts "fanin to out1 flat: [llength $fi1]"
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set fi2 [get_fanin -to [get_ports out1] -only_cells]
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puts "fanin to out1 cells: [llength $fi2]"
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set fi3 [get_fanin -to [get_ports out1] -startpoints_only]
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puts "fanin to out1 startpoints: [llength $fi3]"
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set fo1 [get_fanout -from [get_ports in1] -flat]
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puts "fanout from in1 flat: [llength $fo1]"
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set fo2 [get_fanout -from [get_ports in1] -only_cells]
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puts "fanout from in1 cells: [llength $fo2]"
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set fo3 [get_fanout -from [get_ports in1] -endpoints_only]
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puts "fanout from in1 endpoints: [llength $fo3]"
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# Through different paths
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set fi_out2 [get_fanin -to [get_ports out2] -flat]
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puts "fanin to out2 flat: [llength $fi_out2]"
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set fo_in2 [get_fanout -from [get_ports in2] -flat]
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puts "fanout from in2 flat: [llength $fo_in2]"
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set fo_in3 [get_fanout -from [get_ports in3] -flat]
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puts "fanout from in3 flat: [llength $fo_in3]"
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# Different trace_arcs modes
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set fi_timing [get_fanin -to [get_ports out1] -flat -trace_arcs timing]
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puts "fanin timing: [llength $fi_timing]"
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set fi_all [get_fanin -to [get_ports out1] -flat -trace_arcs all]
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puts "fanin all: [llength $fi_all]"
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set fo_timing [get_fanout -from [get_ports in1] -flat -trace_arcs timing]
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puts "fanout timing: [llength $fo_timing]"
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set fo_all [get_fanout -from [get_ports in1] -flat -trace_arcs all]
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puts "fanout all: [llength $fo_all]"
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#---------------------------------------------------------------
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# Detailed timing through hierarchy
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# Exercises: arc evaluation, path delay calculation
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#---------------------------------------------------------------
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puts "--- timing reports ---"
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report_checks -from [get_ports in1] -to [get_ports out1]
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report_checks -from [get_ports in2] -to [get_ports out1]
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report_checks -from [get_ports in3] -to [get_ports out2]
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report_checks -path_delay min
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report_checks -path_delay max
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# Detailed reports with various fields
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report_checks -fields {slew cap input_pins nets fanout}
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report_checks -format full_clock
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report_checks -format full_clock_expanded
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# Reports with endpoint/group counts
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report_checks -endpoint_count 3
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report_checks -group_count 2
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#---------------------------------------------------------------
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# Network modification in hierarchical context
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#---------------------------------------------------------------
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puts "--- network modify in hierarchy ---"
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set new_buf [make_instance hier_test_buf NangateOpenCellLibrary/BUF_X1]
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set new_inv [make_instance hier_test_inv NangateOpenCellLibrary/INV_X1]
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set new_net1 [make_net hier_test_net1]
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set new_net2 [make_net hier_test_net2]
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# Connect new instances
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connect_pin hier_test_net1 hier_test_buf/A
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connect_pin hier_test_net2 hier_test_buf/Z
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connect_pin hier_test_net2 hier_test_inv/A
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# Disconnect
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disconnect_pin hier_test_net1 hier_test_buf/A
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disconnect_pin hier_test_net2 hier_test_buf/Z
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disconnect_pin hier_test_net2 hier_test_inv/A
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# Clean up
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delete_instance hier_test_buf
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delete_instance hier_test_inv
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delete_net hier_test_net1
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delete_net hier_test_net2
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#---------------------------------------------------------------
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# Register queries
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#---------------------------------------------------------------
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puts "--- register queries ---"
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set regs [all_registers]
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puts "all_registers: [llength $regs]"
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set reg_data [all_registers -data_pins]
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puts "data_pins: [llength $reg_data]"
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set reg_clk [all_registers -clock_pins]
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puts "clock_pins: [llength $reg_clk]"
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set reg_out [all_registers -output_pins]
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puts "output_pins: [llength $reg_out]"
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