308 lines
8.6 KiB
Tcl
308 lines
8.6 KiB
Tcl
# OpenSTA, Static Timing Analyzer
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# Copyright (c) 2024, Parallax Software, Inc.
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#
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# This program is free software: you can redistribute it and/or modify
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# it under the terms of the GNU General Public License as published by
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# the Free Software Foundation, either version 3 of the License, or
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# (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program. If not, see <https://www.gnu.org/licenses/>.
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namespace eval sta {
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################################################################
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#
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# Non-SDC commands
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#
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################################################################
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define_cmd_args "get_fanin" \
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{-to sink_list [-flat] [-only_cells] [-startpoints_only]\
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[-levels level_count] [-pin_levels pin_count]\
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[-trace_arcs timing|enabled|all]}
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proc get_fanin { args } {
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parse_key_args "get_fanin" args \
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keys {-to -levels -pin_levels -trace_arcs} \
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flags {-flat -only_cells -startpoints_only}
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if { [llength $args] != 0 } {
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cmd_usage_error "get_fanin"
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}
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if { ![info exists keys(-to)] } {
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cmd_usage_error "get_fanin"
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}
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parse_port_pin_net_arg $keys(-to) pins nets
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foreach net $nets {
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lappend pins [net_driver_pins $net]
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}
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set flat [info exists flags(-flat)]
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set only_insts [info exists flags(-only_cells)]
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set startpoints_only [info exists flags(-startpoints_only)]
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set inst_levels 0
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if { [info exists keys(-levels)] } {
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set inst_levels $keys(-levels)
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}
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set pin_levels 0
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if { [info exists keys(-pin_levels)] } {
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set pin_levels $keys(-pin_levels)
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}
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set thru_disabled 0
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set thru_constants 0
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if { [info exists keys(-trace_arcs)] } {
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set trace_arcs $keys(-trace_arcs)
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if { $trace_arcs == "timing" } {
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set thru_disabled 0
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set thru_constants 0
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} elseif { $trace_arcs == "enabled" } {
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set thru_disabled 0
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set thru_constants 0
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} elseif { $trace_arcs == "all" } {
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set thru_disabled 1
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set thru_constants 1
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} else {
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cmd_usage_error "get_fanin"
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}
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}
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if { $only_insts } {
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return [find_fanin_insts $pins $flat $startpoints_only \
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$inst_levels $pin_levels $thru_disabled $thru_constants]
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} else {
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return [find_fanin_pins $pins $flat $startpoints_only \
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$inst_levels $pin_levels $thru_disabled $thru_constants]
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}
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}
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################################################################
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define_cmd_args "get_fanout" \
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{-from source_list [-flat] [-only_cells] [-endpoints_only]\
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[-levels level_count] [-pin_levels pin_count]\
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[-trace_arcs timing|enabled|all]}
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proc get_fanout { args } {
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parse_key_args "get_fanout" args \
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keys {-from -levels -pin_levels -trace_arcs} \
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flags {-flat -only_cells -endpoints_only}
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if { [llength $args] != 0 } {
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cmd_usage_error "get_fanout"
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}
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parse_port_pin_net_arg $keys(-from) pins nets
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foreach net $nets {
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lappend pins [net_load_pins $net]
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}
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set flat [info exists flags(-flat)]
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set only_insts [info exists flags(-only_cells)]
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set endpoints_only [info exists flags(-endpoints_only)]
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set inst_levels 0
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if { [info exists keys(-levels)] } {
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set inst_levels $keys(-levels)
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}
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set pin_levels 0
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if { [info exists keys(-pin_levels)] } {
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set pin_levels $keys(-pin_levels)
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}
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set thru_disabled 0
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set thru_constants 0
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if { [info exists keys(-trace_arcs)] } {
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set trace_arcs $keys(-trace_arcs)
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if { $trace_arcs == "timing" } {
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set thru_disabled 0
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set thru_constants 0
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} elseif { $trace_arcs == "enabled" } {
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set thru_disabled 0
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set thru_constants 0
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} elseif { $trace_arcs == "all" } {
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set thru_disabled 1
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set thru_constants 1
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} else {
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cmd_usage_error "get_fanout"
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}
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}
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if { $only_insts } {
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return [find_fanout_insts $pins $flat $endpoints_only \
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$inst_levels $pin_levels $thru_disabled $thru_constants]
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} else {
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return [find_fanout_pins $pins $flat $endpoints_only \
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$inst_levels $pin_levels $thru_disabled $thru_constants]
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}
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}
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################################################################
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define_cmd_args "get_timing_edges" \
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{[-from from_pin] [-to to_pin] [-of_objects objects] [-filter expr]}
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proc get_timing_edges { args } {
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return [get_timing_edges_cmd "get_timing_edges" $args]
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}
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proc get_timing_edges_cmd { cmd cmd_args } {
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parse_key_args $cmd cmd_args \
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keys {-from -to -of_objects -filter} flags {}
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check_argc_eq0 $cmd $cmd_args
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set arcs {}
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if { [info exists keys(-of_objects)] } {
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if { [info exists keys(-from)] \
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|| [info exists keys(-from)] } {
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sta_error 540 "-from/-to arguments not supported with -of_objects."
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}
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set arcs [get_timing_arcs_objects $keys(-of_objects)]
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} elseif { [info exists keys(-from)] \
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&& [info exists keys(-to)] } {
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set arcs [get_timing_arcs_from_to \
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[get_port_pin_error "from" $keys(-from)] \
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[get_port_pin_error "to" $keys(-to)]]
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} elseif { [info exists keys(-from)] } {
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set arcs [get_timing_arcs_from $keys(-from)]
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} elseif { [info exists keys(-to)] } {
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set arcs [get_timing_arcs_to $keys(-to)]
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} else {
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cmd_usage_error $cmd
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}
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if [info exists keys(-filter)] {
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set arcs [filter_objs $keys(-filter) $arcs filter_timing_arcs "timing arc"]
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}
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return $arcs
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}
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proc get_timing_arcs_objects { object_arg } {
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parse_libcell_inst_arg $object_arg libcells insts
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if { $insts != {} } {
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set edges {}
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foreach inst $insts {
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lappend edges [instance_edges $inst]
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}
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return $edges
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} elseif { $libcells != {} } {
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set arc_sets {}
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foreach libcell $libcells {
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lappend arc_sets [$libcell timing_arc_sets]
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}
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return $arc_sets
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}
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}
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proc instance_edges { inst } {
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set edges {}
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set pin_iter [$inst pin_iterator]
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while {[$pin_iter has_next]} {
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set pin [$pin_iter next]
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foreach vertex [$pin vertices] {
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set edge_iter [$vertex out_edge_iterator]
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while {[$edge_iter has_next]} {
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set edge [$edge_iter next]
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if { [$edge role] != "wire" } {
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lappend edges $edge
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}
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}
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$edge_iter finish
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}
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}
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$pin_iter finish
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return $edges
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}
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proc get_timing_arcs_from_to { from_pin_arg to_pin_arg } {
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set edges {}
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set from_pin [get_port_pin_error "from" $from_pin_arg]
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set to_pin [get_port_pin_error "to" $to_pin_arg]
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foreach from_vertex [$from_pin vertices] {
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foreach to_vertex [$to_pin vertices] {
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set edge_iter [$from_vertex out_edge_iterator]
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while {[$edge_iter has_next]} {
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set edge [$edge_iter next]
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if { [$edge to] == $to_vertex } {
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lappend edges $edge
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}
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}
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$edge_iter finish
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}
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}
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return $edges
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}
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proc get_timing_arcs_from { from_pin_arg } {
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set from_pin [get_port_pin_error "from" $from_pin_arg]
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set edges {}
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foreach from_vertex [$from_pin vertices] {
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set edge_iter [$from_vertex out_edge_iterator]
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while {[$edge_iter has_next]} {
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set edge [$edge_iter next]
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lappend edges $edge
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}
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$edge_iter finish
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}
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return $edges
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}
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proc get_timing_arcs_to { to_pin_arg } {
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set to_pin [get_port_pin_error "to" $to_pin_arg]
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set edges {}
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foreach to_vertex [$to_pin vertices] {
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set edge_iter [$to_vertex in_edge_iterator]
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while {[$edge_iter has_next]} {
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set edge [$edge_iter next]
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lappend edges $edge
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}
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$edge_iter finish
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}
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return $edges
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}
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################################################################
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define_cmd_args "report_clock_properties" {[clocks]}
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proc_redirect report_clock_properties {
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check_argc_eq0or1 "report_clock_properties" $args
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update_generated_clks
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report_line "Clock Period Waveform"
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report_line "----------------------------------------------------"
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if { [llength $args] == 0 } {
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foreach clk [all_clocks] {
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report_clock1 $clk
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}
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} else {
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foreach clk [get_clocks_warn "clock_name" [lindex $args 0]] {
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report_clock1 $clk
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}
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}
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}
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proc report_clock1 { clk } {
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global sta_report_default_digits
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if { [$clk waveform_valid] } {
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set digits $sta_report_default_digits
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set waveform [$clk waveform]
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if { $waveform == {} } {
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set wave " "
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} else {
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set wave ""
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foreach edge $waveform {
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set wave "$wave[format "%10s" [format_time $edge $digits]]"
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}
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}
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if {[$clk is_generated]} {
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set generated " (generated)"
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} else {
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set generated ""
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}
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report_line "[format %-20s [get_name $clk]][format %10s [format_time [$clk period] $digits]] $wave$generated"
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}
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}
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# sta namespace end.
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}
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