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Deepashree Sengupta c887b2e4b3 Bias pin handling (#409) 
* Update STA to exclude bias pins from timing graph and subsequently in write_verilog

Signed-off-by: dsengupta0628 <[email protected]>

* unnecessary space in orig verilog

Signed-off-by: dsengupta0628 <[email protected]>

* Update to use well supplies rather than bias pins

Signed-off-by: dsengupta0628 <[email protected]>

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Signed-off-by: dsengupta0628 <[email protected]>
2026-04-07 11:00:01 -07:00
..
ConcreteLibrary.cc
Library/Cell name/filename args string_view
2026-04-03 11:22:38 -07:00
ConcreteNetwork.cc
string squash
2026-03-28 19:13:35 -07:00
HpinDrvrLoad.cc
use std::format squash
2026-03-16 15:01:38 -07:00
Link.tcl
update copyright
2026-03-10 14:57:45 -07:00
Network.cc
string squash
2026-03-28 19:13:35 -07:00
Network.i
string squash
2026-03-28 19:13:35 -07:00
Network.tcl
rm deprecated functions
2026-03-10 14:57:45 -07:00
NetworkCmp.cc
string squash
2026-03-28 19:13:35 -07:00
NetworkEdit.i
update copyright
2026-03-10 14:57:45 -07:00
NetworkEdit.tcl
update copyright
2026-03-10 14:57:45 -07:00
ParseBus.cc
use std::format squash
2026-03-16 15:01:38 -07:00
PortDirection.cc
Bias pin handling (#409)
2026-04-07 11:00:01 -07:00
SdcNetwork.cc
string squash
2026-03-28 19:13:35 -07:00
VerilogNamespace.cc
string squash
2026-03-28 19:13:35 -07:00