65 lines
2.3 KiB
Tcl
65 lines
2.3 KiB
Tcl
# Test 7: Write hierarchical design with removes
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# Exercises: findHierChildren, writeChild remove path
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source ../../test/helpers.tcl
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suppress_msg 1140
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proc assert_file_not_contains {path token} {
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set in [open $path r]
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set text [read $in]
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close $in
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if {[string first $token $text] >= 0} {
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error "did not expect '$token' in $path"
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}
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}
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#---------------------------------------------------------------
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# Test 7: Write hierarchical design with removes
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# Exercises: findHierChildren, writeChild remove path
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#---------------------------------------------------------------
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puts "--- Test 7: hierarchical with removes ---"
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read_liberty ../../test/nangate45/Nangate45_typ.lib
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read_verilog ../../network/test/network_hier_test.v
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link_design network_hier_test
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set out_h_rm [make_result_file verilog_remove_hier_buf.v]
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write_verilog -remove_cells {BUF_X1} $out_h_rm
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assert_file_nonempty $out_h_rm
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assert_file_contains $out_h_rm "module network_hier_test"
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assert_file_not_contains $out_h_rm "BUF_X1"
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set out_h_rm2 [make_result_file verilog_remove_hier_and.v]
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write_verilog -remove_cells {AND2_X1 INV_X1} $out_h_rm2
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assert_file_nonempty $out_h_rm2
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assert_file_contains $out_h_rm2 "module network_hier_test"
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assert_file_not_contains $out_h_rm2 "AND2_X1"
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assert_file_not_contains $out_h_rm2 "INV_X1"
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diff_files verilog_remove_hier_buf.vok $out_h_rm
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diff_files verilog_remove_hier_and.vok $out_h_rm2
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# Read back hierarchical with removes
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read_liberty ../../test/nangate45/Nangate45_typ.lib
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read_verilog $out_h_rm
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link_design network_hier_test
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set rt_h_cells [get_cells *]
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puts "hier roundtrip cells: [llength $rt_h_cells]"
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if {[llength $rt_h_cells] == 0} {
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error "roundtrip hierarchy has no cells"
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}
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set rt_h_hier [get_cells -hierarchical *]
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puts "hier roundtrip hier cells: [llength $rt_h_hier]"
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if {[llength $rt_h_hier] < [llength $rt_h_cells]} {
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error "hierarchical cell count is smaller than flat cell count"
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}
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create_clock -name clk -period 10 [get_ports clk]
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set_input_delay -clock clk 0 [get_ports {in1 in2 in3}]
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set_output_delay -clock clk 0 [get_ports {out1 out2}]
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set_input_transition 0.1 [all_inputs]
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with_output_to_variable hier_rep { report_checks -path_delay max }
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if {![regexp {Path Type:\s+max} $hier_rep]} {
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error "hierarchical remove_cells roundtrip timing report missing max path"
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}
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