28 lines
1.1 KiB
Tcl
28 lines
1.1 KiB
Tcl
# Test 5: Write supply/tristate design (special port directions)
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# Exercises: verilogPortDir for tristate/supply, writePortDcls
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source ../../test/helpers.tcl
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#---------------------------------------------------------------
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# Test 5: Write supply/tristate design (special port directions)
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# Exercises: verilogPortDir for tristate/supply, writePortDcls
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# tristate handling, writeAssigns for output aliases
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#---------------------------------------------------------------
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puts "--- Test 5: write supply/tristate design ---"
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read_liberty ../../test/nangate45/Nangate45_typ.lib
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read_verilog verilog_supply_tristate.v
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link_design verilog_supply_tristate
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set out7 [make_result_file verilog_escaped_supply.v]
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write_verilog $out7
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assert_file_nonempty $out7
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assert_file_contains $out7 "module verilog_supply_tristate"
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assert_file_contains $out7 "tri out1;"
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assert_file_contains $out7 "assign out3 = n6;"
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set out8 [make_result_file verilog_escaped_supply_pwr.v]
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write_verilog -include_pwr_gnd $out8
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assert_file_nonempty $out8
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assert_file_contains $out8 "module verilog_supply_tristate"
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assert_file_contains $out8 "wire gnd_net;"
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assert_file_contains $out8 "wire vdd_net;"
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