42 lines
1.3 KiB
Tcl
42 lines
1.3 KiB
Tcl
# Test 4: Write hierarchical design
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# Exercises: findHierChildren, writeModule for sub-modules, sorted child output
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source ../../test/helpers.tcl
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suppress_msg 1140
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#---------------------------------------------------------------
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# Test 4: Write hierarchical design
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# Exercises: findHierChildren, writeModule for sub-modules,
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# sorted child output
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#---------------------------------------------------------------
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puts "--- Test 4: write hierarchical design ---"
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read_liberty ../../test/nangate45/Nangate45_typ.lib
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read_verilog ../../network/test/network_hier_test.v
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link_design network_hier_test
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set out5 [make_result_file verilog_escaped_hier.v]
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write_verilog $out5
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set out6 [make_result_file verilog_escaped_hier_pwr.v]
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write_verilog -include_pwr_gnd $out6
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# Roundtrip hierarchical
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read_liberty ../../test/nangate45/Nangate45_typ.lib
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read_verilog $out5
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link_design network_hier_test
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set rt3_cells [get_cells *]
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puts "hier roundtrip cells: [llength $rt3_cells]"
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set rt3_nets [get_nets *]
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puts "hier roundtrip nets: [llength $rt3_nets]"
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set rt3_ports [get_ports *]
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puts "hier roundtrip ports: [llength $rt3_ports]"
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# Timing after hierarchical roundtrip
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create_clock -name clk -period 10 [get_ports clk]
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set_input_delay -clock clk 0 [get_ports {in1 in2 in3}]
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set_output_delay -clock clk 0 [get_ports {out1 out2}]
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set_input_transition 0.1 [all_inputs]
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report_checks
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