44 lines
606 B
Plaintext
44 lines
606 B
Plaintext
module verilog_assign_test (clk,
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in1,
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in2,
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in3,
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out1,
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out2,
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out3);
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input clk;
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input in1;
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input in2;
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input in3;
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output out1;
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output out2;
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output out3;
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wire n1;
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wire n2;
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wire n3;
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wire n4;
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wire n5;
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AND2_X1 and1 (.A1(n1),
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.A2(n2),
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.ZN(n3));
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BUF_X1 buf1 (.A(in1),
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.Z(n1));
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BUF_X1 buf2 (.A(in2),
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.Z(n2));
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INV_X1 inv1 (.A(n3),
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.ZN(n4));
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OR2_X1 or1 (.A1(n4),
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.A2(in3),
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.ZN(n5));
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DFF_X1 reg1 (.D(n3),
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.CK(clk),
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.Q(out1));
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DFF_X1 reg2 (.D(n5),
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.CK(clk),
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.Q(out2));
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DFF_X1 reg3 (.D(in3),
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.CK(clk),
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.Q(out3));
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endmodule
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