OpenSTA/verilog
James Cherry 8287aec5f6 Verilog make pins for liberty pg_pins resolves #326
commit b4a89c93965c49a8685fd41cb6aee10635d7a7f3
Author: James Cherry <cherry@parallaxsw.com>
Date:   Fri Nov 7 11:48:10 2025 -0700

    pg_ -> PwrGnd

    Signed-off-by: James Cherry <cherry@parallaxsw.com>

commit 12ddba4bf220cec8459c15e483a871b13e507bf2
Author: James Cherry <cherry@parallaxsw.com>
Date:   Fri Nov 7 08:56:02 2025 -0700

    pg_port

    Signed-off-by: James Cherry <cherry@parallaxsw.com>

Signed-off-by: James Cherry <cherry@parallaxsw.com>
2025-11-07 11:55:43 -07:00
..
Verilog.i update copyright 2025-01-21 18:54:33 -07:00
Verilog.tcl update copyright 2025-01-21 18:54:33 -07:00
VerilogLex.ll Recognize some basic specify blocks and ignore them (#309) 2025-10-12 14:11:00 -07:00
VerilogParse.yy Recognize some basic specify blocks and ignore them (#309) 2025-10-12 14:11:00 -07:00
VerilogReader.cc Verilog make pins for liberty pg_pins resolves #326 2025-11-07 11:55:43 -07:00
VerilogReader.hh remove using std from headers 2025-04-11 16:59:48 -07:00
VerilogReaderPvt.hh remove using std from headers 2025-04-11 16:59:48 -07:00
VerilogScanner.hh LibExpr/spef/saif c++ parsers 2025-02-01 14:49:30 -08:00
VerilogWriter.cc remove using std from headers 2025-04-11 16:59:48 -07:00