54 lines
1.6 KiB
Tcl
54 lines
1.6 KiB
Tcl
# Test advanced verilog writer options - Nangate45 write
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source ../../test/helpers.tcl
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proc assert_file_nonempty {path} {
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if {![file exists $path]} {
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error "expected non-empty file: $path"
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}
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set in [open $path r]
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set text [read $in]
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close $in
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if {[string length $text] <= 0} {
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error "expected non-empty file: $path"
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}
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}
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proc assert_file_contains {path token} {
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set in [open $path r]
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set text [read $in]
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close $in
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if {[string first $token $text] < 0} {
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error "expected '$token' in $path"
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}
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}
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#---------------------------------------------------------------
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# Test 4: Write verilog for Nangate45 design
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#---------------------------------------------------------------
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puts "--- Test 4: Nangate45 write ---"
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read_liberty ../../test/nangate45/Nangate45_typ.lib
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read_verilog verilog_test1.v
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link_design verilog_test1
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set out7 [make_result_file verilog_advanced_out7.v]
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write_verilog $out7
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assert_file_nonempty $out7
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diff_files verilog_advanced_out7.vok $out7
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assert_file_contains $out7 "module verilog_test1"
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assert_file_contains $out7 "BUF_X1"
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set out8 [make_result_file verilog_advanced_out8.v]
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write_verilog -include_pwr_gnd $out8
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assert_file_nonempty $out8
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diff_files verilog_advanced_out8.vok $out8
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assert_file_contains $out8 "module verilog_test1"
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create_clock -name clk -period 10 [get_ports clk]
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set_input_delay -clock clk 0 [get_ports in1]
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set_output_delay -clock clk 0 [get_ports out1]
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set_input_transition 0.1 [all_inputs]
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with_output_to_variable ng_rep { report_checks -path_delay max }
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if {![regexp {Path Type:\s+max} $ng_rep]} {
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error "writer_nangate timing report missing max path"
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}
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