129 lines
4.2 KiB
Tcl
129 lines
4.2 KiB
Tcl
# Test verilog with supply0, supply1, tri-state, wire assign in decl,
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# net constants, part selects, and multiple reads.
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# Targets VerilogReader.cc uncovered paths:
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# supply0/supply1 dcl
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# tri dcl as modifier for output
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# wire assign in declaration (makeDclArg with assign)
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# VerilogNetConstant (makeNetConstant)
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# makeNetPartSelect paths
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# linkNetwork: supply0/supply1 constant net paths
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# mergeAssignNet path
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# Also targets VerilogWriter.cc:
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# verilogPortDir for tristate direction
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# writeAssigns path
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# writeWireDcls with bus wires
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# writePortDcls with tristate direction
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source ../../test/helpers.tcl
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suppress_msg 1140
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#---------------------------------------------------------------
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# Test 1: Read verilog with supply0/supply1/tri
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#---------------------------------------------------------------
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puts "--- Test 1: supply0/supply1/tri read ---"
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read_liberty ../../test/nangate45/Nangate45_typ.lib
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read_verilog verilog_supply_tristate.v
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link_design verilog_supply_tristate
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set cells [get_cells *]
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puts "cells: [llength $cells]"
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set nets [get_nets *]
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puts "nets: [llength $nets]"
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set ports [get_ports *]
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puts "ports: [llength $ports]"
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# Query individual ports
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foreach pname {clk in1 in2 in3 en out1 out2 out3} {
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set p [get_ports $pname]
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puts "$pname dir=[get_property $p direction]"
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}
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# Query bus ports
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set bus_ports [get_ports outbus*]
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puts "outbus* ports: [llength $bus_ports]"
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# Query individual bus bits
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foreach i {0 1 2 3} {
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set p [get_ports "outbus\[$i\]"]
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puts "outbus\[$i\] dir=[get_property $p direction]"
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}
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#---------------------------------------------------------------
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# Test 2: Set up timing and exercise assign connectivity
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#---------------------------------------------------------------
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puts "--- Test 2: timing with supply/tri ---"
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create_clock -name clk -period 10 [get_ports clk]
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set_input_delay -clock clk 0 [get_ports {in1 in2 in3 en}]
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set_output_delay -clock clk 0 [get_ports {out1 out2 out3}]
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set_output_delay -clock clk 0 [get_ports {outbus[0] outbus[1] outbus[2] outbus[3]}]
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set_input_transition 10 {in1 in2 in3 en clk}
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report_checks
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report_checks -path_delay min
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# Paths through assign
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report_checks -from [get_ports in1] -to [get_ports out1]
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report_checks -from [get_ports in3] -to [get_ports out3]
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report_checks -from [get_ports in3] -to [get_ports {outbus[0]}]
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report_checks -fields {slew cap input_pins nets fanout}
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#---------------------------------------------------------------
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# Test 3: report_net for assign-related nets
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#---------------------------------------------------------------
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puts "--- Test 3: report_net ---"
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foreach net_name {n1 n2 n3 n4 n5 n6} {
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report_net $net_name
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puts "report_net $net_name: done"
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}
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# Report instances
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foreach inst_name {buf1 buf2 inv1 and1 or1 buf3 reg1 reg2 reg3} {
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report_instance $inst_name
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}
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#---------------------------------------------------------------
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# Test 4: write_verilog exercises writer paths
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#---------------------------------------------------------------
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puts "--- Test 4: write_verilog ---"
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set out1 [make_result_file verilog_supply_tri_out.v]
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write_verilog $out1
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set out2 [make_result_file verilog_supply_tri_pwr.v]
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write_verilog -include_pwr_gnd $out2
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#---------------------------------------------------------------
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# Test 5: Multiple read_verilog (re-read exercises deleteModules paths)
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#---------------------------------------------------------------
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puts "--- Test 5: re-read verilog ---"
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read_liberty ../../test/nangate45/Nangate45_typ.lib
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read_verilog verilog_supply_tristate.v
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link_design verilog_supply_tristate
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set cells2 [get_cells *]
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puts "re-read cells: [llength $cells2]"
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set nets2 [get_nets *]
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puts "re-read nets: [llength $nets2]"
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#---------------------------------------------------------------
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# Test 6: Read verilog with constants (1'b0, 1'b1)
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#---------------------------------------------------------------
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puts "--- Test 6: fanin/fanout ---"
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set fi [get_fanin -to [get_ports out1] -flat]
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puts "fanin to out1: [llength $fi]"
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set fo [get_fanout -from [get_ports in1] -flat]
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puts "fanout from in1: [llength $fo]"
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set fi_cells [get_fanin -to [get_ports out1] -only_cells]
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puts "fanin cells to out1: [llength $fi_cells]"
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set fo_cells [get_fanout -from [get_ports in1] -only_cells]
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puts "fanout cells from in1: [llength $fo_cells]"
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