350 lines
8.4 KiB
Plaintext
350 lines
8.4 KiB
Plaintext
--- Test 1: supply0/supply1/tri read ---
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cells: 12
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nets: 25
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ports: 12
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clk dir=input
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in1 dir=input
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in2 dir=input
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in3 dir=input
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en dir=input
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out1 dir=tristate
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out2 dir=output
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out3 dir=output
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outbus* ports: 4
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outbus[0] dir=output
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outbus[1] dir=output
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outbus[2] dir=output
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outbus[3] dir=output
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--- Test 2: timing with supply/tri ---
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Startpoint: in3 (input port clocked by clk)
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Endpoint: reg3 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 v input external delay
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0.00 0.00 v in3 (in)
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0.00 0.00 v reg3/D (DFF_X1)
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0.00 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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10.00 ^ reg3/CK (DFF_X1)
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-3.03 6.97 library setup time
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6.97 data required time
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---------------------------------------------------------
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6.97 data required time
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-0.00 data arrival time
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---------------------------------------------------------
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6.97 slack (MET)
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Startpoint: in3 (input port clocked by clk)
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Endpoint: reg3 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: min
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 v input external delay
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0.00 0.00 v in3 (in)
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0.00 0.00 v reg3/D (DFF_X1)
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0.00 data arrival time
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 clock reconvergence pessimism
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0.00 ^ reg3/CK (DFF_X1)
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9.01 9.01 library hold time
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9.01 data required time
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---------------------------------------------------------
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9.01 data required time
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-0.00 data arrival time
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---------------------------------------------------------
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-9.01 slack (VIOLATED)
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No paths found.
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Startpoint: in3 (input port clocked by clk)
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Endpoint: out3 (output port clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 v input external delay
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0.00 0.00 v in3 (in)
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1.67 1.67 ^ inv1/ZN (INV_X1)
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-0.02 1.66 ^ or1/ZN (OR2_X1)
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0.03 1.69 ^ buf3/Z (BUF_X1)
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0.00 1.69 ^ out3 (out)
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1.69 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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0.00 10.00 output external delay
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10.00 data required time
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---------------------------------------------------------
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10.00 data required time
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-1.69 data arrival time
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---------------------------------------------------------
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8.31 slack (MET)
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No paths found.
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Warning 168: verilog_supply_tristate.tcl line 1, unknown field nets.
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Startpoint: in3 (input port clocked by clk)
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Endpoint: reg3 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: max
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Fanout Cap Slew Delay Time Description
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-----------------------------------------------------------------------------
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0.00 0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 v input external delay
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2 2.61 10.00 0.00 0.00 v in3 (in)
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10.00 0.00 0.00 v reg3/D (DFF_X1)
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0.00 data arrival time
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0.00 10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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10.00 ^ reg3/CK (DFF_X1)
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-3.03 6.97 library setup time
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6.97 data required time
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-----------------------------------------------------------------------------
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6.97 data required time
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-0.00 data arrival time
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-----------------------------------------------------------------------------
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6.97 slack (MET)
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--- Test 3: report_net ---
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Net n1
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Pin capacitance: 1.94-2.06
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Wire capacitance: 0.00
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Total capacitance: 1.94-2.06
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Number of drivers: 1
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Number of loads: 2
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Number of pins: 3
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Driver pins
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buf1/Z output (BUF_X1)
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Load pins
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and1/A1 input (AND2_X1) 0.87-0.92
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reg4/D input (DFF_X1) 1.06-1.14
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report_net n1: done
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Net n2
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Pin capacitance: 1.96-2.11
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Wire capacitance: 0.00
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Total capacitance: 1.96-2.11
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Number of drivers: 1
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Number of loads: 2
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Number of pins: 3
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Driver pins
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buf2/Z output (BUF_X1)
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Load pins
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and1/A2 input (AND2_X1) 0.89-0.97
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reg5/D input (DFF_X1) 1.06-1.14
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report_net n2: done
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Net n3
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Pin capacitance: 1.85-2.09
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Wire capacitance: 0.00
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Total capacitance: 1.85-2.09
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Number of drivers: 1
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Number of loads: 2
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Number of pins: 3
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Driver pins
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inv1/ZN output (INV_X1)
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Load pins
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or1/A1 input (OR2_X1) 0.79-0.95
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reg6/D input (DFF_X1) 1.06-1.14
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report_net n3: done
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Net n4
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Pin capacitance: 0.90-0.94
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Wire capacitance: 0.00
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Total capacitance: 0.90-0.94
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Number of drivers: 1
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Number of loads: 1
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Number of pins: 2
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Driver pins
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and1/ZN output (AND2_X1)
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Load pins
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or1/A2 input (OR2_X1) 0.90-0.94
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report_net n4: done
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Net n5
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Pin capacitance: 1.94-2.11
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Wire capacitance: 0.00
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Total capacitance: 1.94-2.11
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Number of drivers: 1
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Number of loads: 2
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Number of pins: 3
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Driver pins
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or1/ZN output (OR2_X1)
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Load pins
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buf3/A input (BUF_X1) 0.88-0.97
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reg1/D input (DFF_X1) 1.06-1.14
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report_net n5: done
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Net n6
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Pin capacitance: 1.06-1.14
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Wire capacitance: 0.00
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Total capacitance: 1.06-1.14
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Number of drivers: 1
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Number of loads: 2
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Number of pins: 3
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Driver pins
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buf3/Z output (BUF_X1)
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Load pins
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out3 output port
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reg2/D input (DFF_X1) 1.06-1.14
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report_net n6: done
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Instance buf1
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Cell: BUF_X1
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Library: NangateOpenCellLibrary
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Path cells: BUF_X1
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Input pins:
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A input in1
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Output pins:
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Z output n1
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Other pins:
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VDD power (unconnected)
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VSS ground (unconnected)
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Instance buf2
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Cell: BUF_X1
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Library: NangateOpenCellLibrary
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Path cells: BUF_X1
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Input pins:
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A input in2
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Output pins:
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Z output n2
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Other pins:
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VDD power (unconnected)
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VSS ground (unconnected)
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Instance inv1
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Cell: INV_X1
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Library: NangateOpenCellLibrary
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Path cells: INV_X1
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Input pins:
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A input in3
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Output pins:
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ZN output n3
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Other pins:
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VDD power (unconnected)
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VSS ground (unconnected)
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Instance and1
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Cell: AND2_X1
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Library: NangateOpenCellLibrary
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Path cells: AND2_X1
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Input pins:
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A1 input n1
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A2 input n2
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Output pins:
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ZN output n4
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Other pins:
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VDD power (unconnected)
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VSS ground (unconnected)
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Instance or1
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Cell: OR2_X1
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Library: NangateOpenCellLibrary
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Path cells: OR2_X1
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Input pins:
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A1 input n3
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A2 input n4
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Output pins:
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ZN output n5
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Other pins:
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VDD power (unconnected)
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VSS ground (unconnected)
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Instance buf3
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Cell: BUF_X1
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Library: NangateOpenCellLibrary
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Path cells: BUF_X1
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Input pins:
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A input n5
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Output pins:
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Z output n6
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Other pins:
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VDD power (unconnected)
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VSS ground (unconnected)
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Instance reg1
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Cell: DFF_X1
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Library: NangateOpenCellLibrary
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Path cells: DFF_X1
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Input pins:
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D input n5
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CK input clk
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Output pins:
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Q output out1
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QN output (unconnected)
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Other pins:
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VDD power (unconnected)
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VSS ground (unconnected)
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IQ internal (unconnected)
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IQN internal (unconnected)
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Instance reg2
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Cell: DFF_X1
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Library: NangateOpenCellLibrary
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Path cells: DFF_X1
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Input pins:
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D input n6
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CK input clk
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Output pins:
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Q output out2
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QN output (unconnected)
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Other pins:
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VDD power (unconnected)
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VSS ground (unconnected)
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IQ internal (unconnected)
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IQN internal (unconnected)
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Instance reg3
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Cell: DFF_X1
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Library: NangateOpenCellLibrary
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Path cells: DFF_X1
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Input pins:
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D input in3
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CK input clk
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Output pins:
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Q output outbus[0]
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QN output (unconnected)
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Other pins:
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VDD power (unconnected)
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VSS ground (unconnected)
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IQ internal (unconnected)
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IQN internal (unconnected)
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--- Test 4: write_verilog ---
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--- Test 5: re-read verilog ---
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re-read cells: 12
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re-read nets: 25
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--- Test 6: fanin/fanout ---
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fanin to out1: 3
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fanout from in1: 13
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fanin cells to out1: 2
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fanout cells from in1: 8
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