26 lines
767 B
Tcl
26 lines
767 B
Tcl
# Test write_verilog should omit bias pins the same way it omits power/ground.
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source ../../test/helpers.tcl
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puts "--- write_verilog bias pins ---"
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read_liberty ../../test/sky130hd/sky130_fd_sc_hd__ss_n40C_1v40.lib
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read_verilog verilog_bias_pins.v
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link_design top
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set outfile [make_result_file verilog_bias_pins_out.v]
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write_verilog $outfile
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set outfile_pwr [make_result_file verilog_bias_pins_pwr.v]
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write_verilog -include_pwr_gnd $outfile_pwr
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set combined_out [make_result_file verilog_bias_pins_combined.v]
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set out_stream [open $combined_out w]
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foreach file [list $outfile $outfile_pwr] {
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set in_stream [open $file r]
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puts -nonewline $out_stream [read $in_stream]
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close $in_stream
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}
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close $out_stream
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diff_files verilog_bias_pins_out.vok $combined_out
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