274 lines
9.2 KiB
Plaintext
274 lines
9.2 KiB
Plaintext
--- thread operations ---
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initial thread_count: 1
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thread_count after set to 2: 2
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thread_count after set to 1: 1
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thread_count after set to 4: 4
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PASS: thread count operations
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--- processor_count ---
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processor_count: 64
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PASS: processor_count positive
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--- memory_usage ---
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PASS: memory_usage non-negative
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--- load design for parallel timing ---
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Warning: util_parallel_misc.tcl line 1, set_input_delay relative to a clock defined on the same port/pin not allowed.
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Startpoint: data_a[6] (input port clocked by clk)
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Endpoint: carry (output port clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 v input external delay
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0.00 0.00 v data_a[6] (in)
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0.06 0.06 v buf_a6/Z (BUF_X1)
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0.03 0.09 v and6/ZN (AND2_X1)
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0.05 0.13 v or_carry/ZN (OR2_X1)
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0.02 0.16 v buf_carry/Z (BUF_X1)
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0.00 0.16 v carry (out)
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0.16 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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0.00 10.00 output external delay
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10.00 data required time
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---------------------------------------------------------
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10.00 data required time
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-0.16 data arrival time
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---------------------------------------------------------
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9.84 slack (MET)
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PASS: report_checks with 1 thread
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Startpoint: data_a[6] (input port clocked by clk)
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Endpoint: carry (output port clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 v input external delay
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0.00 0.00 v data_a[6] (in)
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0.06 0.06 v buf_a6/Z (BUF_X1)
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0.03 0.09 v and6/ZN (AND2_X1)
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0.05 0.13 v or_carry/ZN (OR2_X1)
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0.02 0.16 v buf_carry/Z (BUF_X1)
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0.00 0.16 v carry (out)
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0.16 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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0.00 10.00 output external delay
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10.00 data required time
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---------------------------------------------------------
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10.00 data required time
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-0.16 data arrival time
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---------------------------------------------------------
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9.84 slack (MET)
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PASS: report_checks with 2 threads
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Startpoint: data_a[6] (input port clocked by clk)
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Endpoint: carry (output port clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 v input external delay
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0.00 0.00 v data_a[6] (in)
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0.06 0.06 v buf_a6/Z (BUF_X1)
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0.03 0.09 v and6/ZN (AND2_X1)
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0.05 0.13 v or_carry/ZN (OR2_X1)
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0.02 0.16 v buf_carry/Z (BUF_X1)
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0.00 0.16 v carry (out)
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0.16 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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0.00 10.00 output external delay
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10.00 data required time
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---------------------------------------------------------
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10.00 data required time
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-0.16 data arrival time
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---------------------------------------------------------
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9.84 slack (MET)
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PASS: report_checks with 4 threads
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--- buffer growth test ---
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large capture length: 4827
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PASS: buffer growth
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--- string redirect large ---
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string redirect length: 4827
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PASS: string redirect large
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--- file redirect large ---
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file redirect size: 4827
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PASS: file redirect large
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--- append cycles ---
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appended file size: 2079
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PASS: append cycles
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--- debug with threads ---
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search: find arrivals pass 1
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search: find arrivals to level 90
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search: found 0 arrivals
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Startpoint: data_a[6] (input port clocked by clk)
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Endpoint: carry (output port clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 v input external delay
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0.00 0.00 v data_a[6] (in)
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0.06 0.06 v buf_a6/Z (BUF_X1)
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0.03 0.09 v and6/ZN (AND2_X1)
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0.05 0.13 v or_carry/ZN (OR2_X1)
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0.02 0.16 v buf_carry/Z (BUF_X1)
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0.00 0.16 v carry (out)
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0.16 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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0.00 10.00 output external delay
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10.00 data required time
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---------------------------------------------------------
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10.00 data required time
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-0.16 data arrival time
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---------------------------------------------------------
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9.84 slack (MET)
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PASS: debug search with threads
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delay_calc: find delays to level 90
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delay_calc: found 0 delays
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Startpoint: data_a[6] (input port clocked by clk)
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Endpoint: carry (output port clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 v input external delay
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0.00 0.00 v data_a[6] (in)
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0.06 0.06 v buf_a6/Z (BUF_X1)
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0.03 0.09 v and6/ZN (AND2_X1)
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0.05 0.13 v or_carry/ZN (OR2_X1)
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0.02 0.16 v buf_carry/Z (BUF_X1)
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0.00 0.16 v carry (out)
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0.16 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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0.00 10.00 output external delay
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10.00 data required time
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---------------------------------------------------------
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10.00 data required time
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-0.16 data arrival time
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---------------------------------------------------------
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9.84 slack (MET)
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PASS: debug delay_calc with threads
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--- report_line coverage ---
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single line
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line with special: [ ] { } $ \
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very long line: abcdefghijabcdefghijabcdefghijabcdefghijabcdefghijabcdefghijabcdefghijabcdefghijabcdefghijabcdefghijabcdefghijabcdefghijabcdefghijabcdefghijabcdefghijabcdefghijabcdefghijabcdefghijabcdefghijabcdefghijabcdefghijabcdefghijabcdefghijabcdefghijabcdefghijabcdefghijabcdefghijabcdefghijabcdefghijabcdefghijabcdefghijabcdefghijabcdefghijabcdefghijabcdefghijabcdefghijabcdefghijabcdefghijabcdefghijabcdefghijabcdefghijabcdefghijabcdefghijabcdefghijabcdefghijabcdefghijabcdefghijabcdefghijabcdefghijabcdefghij
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PASS: report_line coverage
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--- format extreme values ---
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format_time(1fs): 0.000000
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format_time(1ms): 1000000.062
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format_capacitance(1aF): 0.001000
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format_resistance(1mOhm): 0.000000
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format_power(1pW): 0.001000
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format_distance(1nm): 0.001000
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PASS: format extreme values
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--- log with design ops ---
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Startpoint: data_a[6] (input port clocked by clk)
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Endpoint: carry (output port clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 v input external delay
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0.00 0.00 v data_a[6] (in)
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0.06 0.06 v buf_a6/Z (BUF_X1)
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0.03 0.09 v and6/ZN (AND2_X1)
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0.05 0.13 v or_carry/ZN (OR2_X1)
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0.02 0.16 v buf_carry/Z (BUF_X1)
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0.00 0.16 v carry (out)
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0.16 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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0.00 10.00 output external delay
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10.00 data required time
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---------------------------------------------------------
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10.00 data required time
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-0.16 data arrival time
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---------------------------------------------------------
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9.84 slack (MET)
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Startpoint: data_b[0] (input port clocked by clk)
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Endpoint: reg0 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: min
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 ^ input external delay
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0.00 0.00 ^ data_b[0] (in)
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0.04 0.04 ^ and0/ZN (AND2_X1)
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0.00 0.04 ^ reg0/D (DFF_X1)
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0.04 data arrival time
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 clock reconvergence pessimism
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0.00 ^ reg0/CK (DFF_X1)
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0.01 0.01 library hold time
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0.01 data required time
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---------------------------------------------------------
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0.01 data required time
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-0.04 data arrival time
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---------------------------------------------------------
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0.04 slack (MET)
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time 1ns
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capacitance 1fF
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resistance 1kohm
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voltage 1v
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current 1mA
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power 1nW
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distance 1um
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PASS: log with design ops
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--- error paths ---
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PASS: caught nonexistent liberty error
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PASS: caught nonexistent verilog error
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PASS: caught nonexistent SPEF error
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PASS: caught nonexistent SDF error
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ALL PASSED
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