523 lines
12 KiB
Plaintext
523 lines
12 KiB
Plaintext
%{
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// OpenSTA, Static Timing Analyzer
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// Copyright (c) 2024, Parallax Software, Inc.
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//
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <https://www.gnu.org/licenses/>.
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#include <cstdlib>
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#include <string>
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#include <iostream>
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#include "PortDirection.hh"
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#include "verilog/VerilogReaderPvt.hh"
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#include "VerilogReader.hh"
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int VerilogLex_lex();
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#define VerilogParse_lex VerilogLex_lex
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// Use yacc generated parser errors.
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#define YYERROR_VERBOSE
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%}
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%union{
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int ival;
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const char *string;
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const char *constant;
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const char *attribute_spec_value;
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sta::VerilogModule *module;
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sta::VerilogStmt *stmt;
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sta::VerilogStmtSeq *stmt_seq;
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sta::PortDirection *port_type;
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sta::VerilogDclArgSeq *dcl_arg_seq;
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sta::VerilogDclArg *dcl_arg;
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sta::VerilogAssign *assign;
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sta::VerilogInst *inst;
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sta::VerilogNet *net;
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sta::VerilogNetBitSelect *net_bit;
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sta::VerilogNetSeq *nets;
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sta::VerilogAttributeEntry *attribute_entry;
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sta::VerilogAttributeEntrySeq *attribute_seq;
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sta::VerilogAttributeStmt *attribute_stmt;
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sta::VerilogAttributeStmtSeq *attribute_stmt_seq;
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}
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%token INT CONSTANT ID STRING MODULE ENDMODULE ASSIGN PARAMETER DEFPARAM
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%token WIRE WAND WOR TRI INPUT OUTPUT INOUT SUPPLY1 SUPPLY0 REG
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%token ATTRIBUTE_OPEN ATTRIBUTE_CLOSED
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%left '-' '+'
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%left '*' '/'
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%left NEG /* negation--unary minus */
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%type <string> ID STRING
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%type <ival> WIRE WAND WOR TRI INPUT OUTPUT INOUT SUPPLY1 SUPPLY0
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%type <ival> ATTRIBUTE_OPEN ATTRIBUTE_CLOSED
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%type <ival> INT parameter_exprs parameter_expr module_begin
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%type <constant> CONSTANT
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%type <attribute_spec_value> attr_spec_value
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%type <port_type> dcl_type port_dcl_type
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%type <stmt> stmt declaration instance parameter parameter_dcls parameter_dcl
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%type <stmt> defparam param_values param_value port_dcl
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%type <stmt_seq> stmts stmt_seq net_assignments continuous_assign port_dcls
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%type <assign> net_assignment
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%type <dcl_arg> dcl_arg
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%type <dcl_arg_seq> dcl_args
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%type <net> port net_scalar net_bit_select net_part_select net_assign_lhs
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%type <net> net_constant net_expr port_ref port_expr named_pin_net_expr
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%type <net> inst_named_pin net_named net_expr_concat
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%type <nets> port_list port_refs inst_ordered_pins
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%type <nets> inst_named_pins net_exprs inst_pins
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%type <attribute_entry> attr_spec
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%type <attribute_seq> attr_specs
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%type <attribute_stmt> attribute_instance
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%type <attribute_stmt_seq> attribute_instance_seq
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%start file
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%{
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%}
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%%
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file:
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modules
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;
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modules:
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// empty
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| modules module
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;
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module_begin:
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MODULE { $<ival>$ = sta::verilog_reader->line(); }
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{ $$ = $<ival>2; }
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;
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module:
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attribute_instance_seq module_begin ID ';' stmts ENDMODULE
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{ sta::verilog_reader->makeModule($3, new sta::VerilogNetSeq, $5, $1, $2);}
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| attribute_instance_seq module_begin ID '(' ')' ';' stmts ENDMODULE
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{ sta::verilog_reader->makeModule($3, new sta::VerilogNetSeq, $7, $1, $2);}
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| attribute_instance_seq module_begin ID '(' port_list ')' ';' stmts ENDMODULE
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{ sta::verilog_reader->makeModule($3, $5, $8, $1, $2); }
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| attribute_instance_seq module_begin ID '(' port_dcls ')' ';' stmts ENDMODULE
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{ sta::verilog_reader->makeModule($3, $5, $8, $1, $2); }
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;
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port_list:
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port
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{ $$ = new sta::VerilogNetSeq;
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$$->push_back($1);
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}
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| port_list ',' port
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{ $1->push_back($3); }
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;
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port:
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port_expr
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| '.' ID '(' ')'
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{ $$=sta::verilog_reader->makeNetNamedPortRefScalar($2, NULL);}
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| '.' ID '(' port_expr ')'
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{ $$=sta::verilog_reader->makeNetNamedPortRefScalar($2, $4);}
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;
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port_expr:
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port_ref
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| '{' port_refs '}'
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{ $$ = sta::verilog_reader->makeNetConcat($2); } ;
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port_refs:
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port_ref
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{ $$ = new sta::VerilogNetSeq;
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$$->push_back($1);
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}
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| port_refs ',' port_ref
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{ $1->push_back($3); }
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;
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port_ref:
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net_scalar
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| net_bit_select
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| net_part_select
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;
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port_dcls:
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port_dcl
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{ $$ = new sta::VerilogStmtSeq;
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$$->push_back($1);
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}
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| port_dcls ',' port_dcl
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{ $$ = $1;
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$1->push_back($3);
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}
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| port_dcls ',' dcl_arg
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{
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sta::VerilogDcl *dcl = dynamic_cast<sta::VerilogDcl*>($1->back());
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dcl->appendArg($3);
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$$ = $1;
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}
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;
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port_dcl:
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attribute_instance_seq port_dcl_type
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{ $<ival>$ = sta::verilog_reader->line(); } dcl_arg
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{ $$ = sta::verilog_reader->makeDcl($2, $4, $1, $<ival>3); }
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| attribute_instance_seq port_dcl_type
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{ $<ival>$ = sta::verilog_reader->line(); } '[' INT ':' INT ']' dcl_arg
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{ $$ = sta::verilog_reader->makeDclBus($2, $5, $7, $9, $1, $<ival>3); }
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;
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port_dcl_type:
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INPUT { $$ = sta::PortDirection::input(); }
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| INPUT WIRE { $$ = sta::PortDirection::input(); }
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| INOUT { $$ = sta::PortDirection::bidirect(); }
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| INOUT REG { $$ = sta::PortDirection::bidirect(); }
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| INOUT WIRE { $$ = sta::PortDirection::bidirect(); }
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| OUTPUT { $$ = sta::PortDirection::output(); }
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| OUTPUT WIRE { $$ = sta::PortDirection::output(); }
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| OUTPUT REG { $$ = sta::PortDirection::output(); }
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;
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stmts:
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// empty
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{ $$ = new sta::VerilogStmtSeq; }
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| stmts stmt
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{ if ($2) $1->push_back($2); }
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| stmts stmt_seq
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// Append stmt_seq to stmts.
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{ sta::VerilogStmtSeq::Iterator iter($2);
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while (iter.hasNext())
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$1->push_back(iter.next());
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delete $2;
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}
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;
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stmt:
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parameter
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| defparam
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| declaration
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| instance
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| error ';'
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{ yyerrok; $$ = NULL; }
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;
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stmt_seq:
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continuous_assign
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;
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/* Parameters are parsed and ignored. */
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parameter:
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PARAMETER parameter_dcls ';'
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{ $$ = NULL; }
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| PARAMETER '[' INT ':' INT ']' parameter_dcls ';'
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{ $$ = NULL; }
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;
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parameter_dcls:
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parameter_dcl
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{ $$ = NULL; }
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| parameter_dcls ',' parameter_dcl
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{ $$ = NULL; }
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;
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parameter_dcl:
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ID '=' parameter_expr
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{ sta::stringDelete($1);
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$$ = NULL;
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}
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| ID '=' STRING
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{ sta::stringDelete($1);
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sta::stringDelete($3);
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$$ = NULL;
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}
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;
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parameter_expr:
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ID
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{ sta::stringDelete($1);
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$$ = 0;
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}
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| '`' ID
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{ sta::stringDelete($2);
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$$ = 0;
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}
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| CONSTANT
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{ sta::stringDelete($1);
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$$ = 0;
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}
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| INT
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| '-' parameter_expr %prec NEG
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{ $$ = - $2; }
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| parameter_expr '+' parameter_expr
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{ $$ = $1 + $3; }
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| parameter_expr '-' parameter_expr
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{ $$ = $1 - $3; }
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| parameter_expr '*' parameter_expr
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{ $$ = $1 * $3; }
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| parameter_expr '/' parameter_expr
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{ $$ = $1 / $3; }
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| '(' parameter_expr ')'
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{ $$ = $2; }
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;
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defparam:
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DEFPARAM param_values ';'
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{ $$ = NULL; }
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;
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param_values:
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param_value
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{ $$ = NULL; }
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| param_values ',' param_value
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{ $$ = NULL; }
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;
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param_value:
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ID '=' parameter_expr
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{ sta::stringDelete($1);
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$$ = NULL;
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}
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| ID '=' STRING
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{ sta::stringDelete($1);
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sta::stringDelete($3);
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$$ = NULL;
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}
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;
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declaration:
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attribute_instance_seq dcl_type { $<ival>$ = sta::verilog_reader->line(); } dcl_args ';'
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{ $$ = sta::verilog_reader->makeDcl($2, $4, $1, $<ival>3); }
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| attribute_instance_seq dcl_type { $<ival>$ = sta::verilog_reader->line(); }
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'[' INT ':' INT ']' dcl_args ';'
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{ $$ = sta::verilog_reader->makeDclBus($2, $5, $7, $9, $1,$<ival>3); }
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;
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dcl_type:
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INPUT { $$ = sta::PortDirection::input(); }
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| INOUT { $$ = sta::PortDirection::bidirect(); }
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| OUTPUT { $$ = sta::PortDirection::output(); }
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| SUPPLY0 { $$ = sta::PortDirection::ground(); }
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| SUPPLY1 { $$ = sta::PortDirection::power(); }
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| TRI { $$ = sta::PortDirection::tristate(); }
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| WAND { $$ = sta::PortDirection::internal(); }
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| WIRE { $$ = sta::PortDirection::internal(); }
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| WOR { $$ = sta::PortDirection::internal(); }
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;
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dcl_args:
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dcl_arg
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{ $$ = new sta::VerilogDclArgSeq;
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$$->push_back($1);
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}
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| dcl_args ',' dcl_arg
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{ $1->push_back($3);
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$$ = $1;
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}
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;
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dcl_arg:
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ID
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{ $$ = sta::verilog_reader->makeDclArg($1); }
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| net_assignment
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{ $$ = sta::verilog_reader->makeDclArg($1); }
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;
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continuous_assign:
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ASSIGN net_assignments ';'
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{ $$ = $2; }
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;
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net_assignments:
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net_assignment
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{ $$ = new sta::VerilogStmtSeq();
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$$->push_back($1);
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}
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| net_assignments ',' net_assignment
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{ $1->push_back($3); }
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;
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net_assignment:
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net_assign_lhs { $<ival>$ = sta::verilog_reader->line(); } '=' net_expr
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{ $$ = sta::verilog_reader->makeAssign($1, $4, $<ival>2); }
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;
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net_assign_lhs:
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net_named
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| net_expr_concat
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;
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instance:
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attribute_instance_seq ID { $<ival>$ = sta::verilog_reader->line(); } ID '(' inst_pins ')' ';'
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{ $$ = sta::verilog_reader->makeModuleInst($2, $4, $6, $1, $<ival>3); }
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| attribute_instance_seq ID { $<ival>$ = sta::verilog_reader->line(); } parameter_values
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ID '(' inst_pins ')' ';'
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{ $$ = sta::verilog_reader->makeModuleInst($2, $5, $7, $1, $<ival>3); }
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;
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parameter_values:
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'#' '(' parameter_exprs ')'
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;
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parameter_exprs:
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parameter_expr
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| '{' parameter_exprs '}'
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{ $$ = $2; }
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| parameter_exprs ',' parameter_expr
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;
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inst_pins:
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// empty
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{ $$ = NULL; }
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| inst_ordered_pins
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| inst_named_pins
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;
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// Positional pin connections.
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inst_ordered_pins:
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net_expr
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{ $$ = new sta::VerilogNetSeq;
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$$->push_back($1);
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}
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| inst_ordered_pins ',' net_expr
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{ $1->push_back($3); }
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;
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// Named pin connections.
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inst_named_pins:
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inst_named_pin
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{ $$ = new sta::VerilogNetSeq;
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$$->push_back($1);
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}
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| inst_named_pins ',' inst_named_pin
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{ $1->push_back($3); }
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;
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// The port reference is split out into cases to special case
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// the most frequent case of .port_scalar(net_scalar).
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inst_named_pin:
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// Scalar port.
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'.' ID '(' ')'
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{ $$ = sta::verilog_reader->makeNetNamedPortRefScalarNet($2); }
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| '.' ID '(' ID ')'
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{ $$ = sta::verilog_reader->makeNetNamedPortRefScalarNet($2, $4); }
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| '.' ID '(' ID '[' INT ']' ')'
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{ $$ = sta::verilog_reader->makeNetNamedPortRefBitSelect($2, $4, $6); }
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| '.' ID '(' named_pin_net_expr ')'
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{ $$ = sta::verilog_reader->makeNetNamedPortRefScalar($2, $4); }
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// Bus port bit select.
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| '.' ID '[' INT ']' '(' ')'
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{ $$ = sta::verilog_reader->makeNetNamedPortRefBit($2, $4, NULL); }
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| '.' ID '[' INT ']' '(' net_expr ')'
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{ $$ = sta::verilog_reader->makeNetNamedPortRefBit($2, $4, $7); }
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// Bus port part select.
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| '.' ID '[' INT ':' INT ']' '(' ')'
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{ $$ = sta::verilog_reader->makeNetNamedPortRefPart($2, $4, $6, NULL); }
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| '.' ID '[' INT ':' INT ']' '(' net_expr ')'
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{ $$ = sta::verilog_reader->makeNetNamedPortRefPart($2, $4, $6, $9); }
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;
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named_pin_net_expr:
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net_part_select
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| net_constant
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| net_expr_concat
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;
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net_named:
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net_scalar
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| net_bit_select
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| net_part_select
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;
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net_scalar:
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ID
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{ $$ = sta::verilog_reader->makeNetScalar($1); }
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;
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net_bit_select:
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ID '[' INT ']'
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{ $$ = sta::verilog_reader->makeNetBitSelect($1, $3); }
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;
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net_part_select:
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ID '[' INT ':' INT ']'
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{ $$ = sta::verilog_reader->makeNetPartSelect($1, $3, $5); }
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;
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net_constant:
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CONSTANT
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{ $$ = sta::verilog_reader->makeNetConstant($1); }
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;
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net_expr_concat:
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'{' net_exprs '}'
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{ $$ = sta::verilog_reader->makeNetConcat($2); }
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;
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net_exprs:
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net_expr
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{ $$ = new sta::VerilogNetSeq;
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$$->push_back($1);
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}
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| net_exprs ',' net_expr
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{ $$->push_back($3); }
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;
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net_expr:
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net_scalar
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| net_bit_select
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| net_part_select
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| net_constant
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| net_expr_concat
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;
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attribute_instance_seq:
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// empty
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{ $$ = new sta::VerilogAttributeStmtSeq; }
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| attribute_instance_seq attribute_instance
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{ if ($2) $1->push_back($2); }
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;
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attribute_instance:
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ATTRIBUTE_OPEN attr_specs ATTRIBUTE_CLOSED
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{ $$ = new sta::VerilogAttributeStmt($2); }
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;
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attr_specs:
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attr_spec
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{ $$ = new sta::VerilogAttributeEntrySeq;
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$$->push_back($1);
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}
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| attr_specs ',' attr_spec
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{ $$->push_back($3); }
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;
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attr_spec:
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ID
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{ $$ = new sta::VerilogAttributeEntry($1, "1"); }
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| ID '=' attr_spec_value
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{ $$ = new sta::VerilogAttributeEntry($1, $3); }
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;
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attr_spec_value:
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CONSTANT
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{ $$ = $1; }
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| STRING
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{ $$ = $1; }
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| INT
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{ $$ = sta::stringCopy(std::to_string($1).c_str()); }
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;
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%%
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