101 lines
3.3 KiB
Tcl
101 lines
3.3 KiB
Tcl
# Test write_path_spice with -subcircuit_file option
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# and various path configurations to exercise uncovered WriteSpice.cc paths:
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# WriteSpice constructor paths
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# writeSubckt, findSubckt paths
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# simulator-specific code paths (ngspice, hspice, xyce)
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# Also targets WritePathSpice.cc:
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# writePathSpice with different -path_args options
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# NOTE: write_gate_spice tests removed - write_gate_spice_cmd SWIG binding
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# is missing. See bug_report_missing_write_gate_spice_cmd.md.
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source ../../test/helpers.tcl
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read_liberty ../../test/nangate45/Nangate45_typ.lib
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read_verilog spice_test2.v
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link_design spice_test2
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create_clock -name clk -period 10 [get_ports clk]
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set_input_delay -clock clk 1.0 [get_ports {in1 in2}]
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set_output_delay -clock clk 1.0 [get_ports {out1 out2}]
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set_input_transition 0.1 [get_ports {in1 in2}]
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puts "--- report_checks ---"
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report_checks
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# Create mock SPICE subcircuit and model files
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set spice_dir [make_result_file spice_subckt_out]
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file mkdir $spice_dir
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set model_file [file join $spice_dir model.sp]
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set model_fh [open $model_file w]
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puts $model_fh "* SPICE model file"
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puts $model_fh ".model nmos nmos level=1"
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puts $model_fh ".model pmos pmos level=1"
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close $model_fh
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set subckt_file [file join $spice_dir subckt.sp]
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set subckt_fh [open $subckt_file w]
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puts $subckt_fh "* SPICE subckt file"
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puts $subckt_fh ".subckt BUF_X1 A Z VDD VSS"
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puts $subckt_fh "M1 Z A VDD VDD pmos W=1u L=100n"
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puts $subckt_fh "M2 Z A VSS VSS nmos W=1u L=100n"
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puts $subckt_fh ".ends"
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puts $subckt_fh ""
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puts $subckt_fh ".subckt INV_X1 A ZN VDD VSS"
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puts $subckt_fh "M1 ZN A VDD VDD pmos W=1u L=100n"
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puts $subckt_fh "M2 ZN A VSS VSS nmos W=1u L=100n"
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puts $subckt_fh ".ends"
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puts $subckt_fh ""
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puts $subckt_fh ".subckt AND2_X1 A1 A2 ZN VDD VSS"
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puts $subckt_fh "M1 ZN A1 VDD VDD pmos W=1u L=100n"
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puts $subckt_fh "M2 ZN A2 VSS VSS nmos W=1u L=100n"
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puts $subckt_fh ".ends"
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puts $subckt_fh ""
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puts $subckt_fh ".subckt OR2_X1 A1 A2 ZN VDD VSS"
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puts $subckt_fh "M1 ZN A1 VDD VDD pmos W=1u L=100n"
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puts $subckt_fh "M2 ZN A2 VSS VSS nmos W=1u L=100n"
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puts $subckt_fh ".ends"
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puts $subckt_fh ""
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puts $subckt_fh ".subckt DFF_X1 D CK Q QN VDD VSS"
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puts $subckt_fh "M1 Q D VDD VDD pmos W=1u L=100n"
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puts $subckt_fh "M2 Q D VSS VSS nmos W=1u L=100n"
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puts $subckt_fh ".ends"
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close $subckt_fh
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#---------------------------------------------------------------
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# write_path_spice with various options
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#---------------------------------------------------------------
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puts "--- write_path_spice to out1 ---"
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set spice_dir2 [file join $spice_dir path_out1]
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file mkdir $spice_dir2
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write_path_spice \
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-path_args {-to out1 -path_delay max} \
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-spice_file [file join $spice_dir2 spice] \
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-lib_subckt_file $subckt_file \
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-model_file $model_file \
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-power VDD \
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-ground VSS
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puts "--- write_path_spice to out2 ---"
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set spice_dir3 [file join $spice_dir path_out2]
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file mkdir $spice_dir3
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write_path_spice \
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-path_args {-to out2 -path_delay max} \
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-spice_file [file join $spice_dir3 spice] \
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-lib_subckt_file $subckt_file \
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-model_file $model_file \
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-power VDD \
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-ground VSS
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puts "--- write_path_spice with ngspice ---"
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set spice_dir4 [file join $spice_dir path_ng]
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file mkdir $spice_dir4
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write_path_spice \
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-path_args {-sort_by_slack} \
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-spice_file [file join $spice_dir4 spice] \
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-lib_subckt_file $subckt_file \
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-model_file $model_file \
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-power VDD \
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-ground VSS \
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-simulator ngspice
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