99 lines
2.9 KiB
Tcl
99 lines
2.9 KiB
Tcl
# Test write_path_spice with GCD sky130 design.
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# Uses a larger design to exercise different cell type handling,
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# multi-input gates, and varied simulator outputs.
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# NOTE: write_gate_spice tests removed - write_gate_spice_cmd SWIG binding
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# is missing. See bug_report_missing_write_gate_spice_cmd.md.
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source ../../test/helpers.tcl
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read_liberty ../../test/sky130hd/sky130_fd_sc_hd__tt_025C_1v80.lib
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read_verilog ../../examples/gcd_sky130hd.v
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link_design gcd
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read_sdc ../../examples/gcd_sky130hd.sdc
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puts "--- baseline timing ---"
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report_checks
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# Create mock SPICE subckt and model files for sky130 cells
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set spice_dir [make_result_file spice_gcd_gate_out]
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file mkdir $spice_dir
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set model_file [file join $spice_dir sky130_model.sp]
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set mfh [open $model_file w]
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puts $mfh "* Sky130 mock model file"
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puts $mfh ".model nfet_01v8 nmos level=1 VTO=0.4 KP=200u"
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puts $mfh ".model pfet_01v8 pmos level=1 VTO=-0.4 KP=100u"
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close $mfh
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# Dynamically generate subckts for all cell types used in the design
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set subckt_file [file join $spice_dir sky130_subckt.sp]
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set sfh [open $subckt_file w]
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puts $sfh "* Sky130 mock subckt file"
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set cell_names [list]
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set all_insts [get_cells *]
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foreach inst $all_insts {
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set cell_ref [get_property $inst ref_name]
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if { [lsearch -exact $cell_names $cell_ref] == -1 } {
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lappend cell_names $cell_ref
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}
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}
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foreach cell_name $cell_names {
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set lib_pins [get_lib_pins */${cell_name}/*]
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if { [llength $lib_pins] == 0 } { continue }
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set ports [list]
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foreach lp $lib_pins {
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lappend ports [get_property $lp name]
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}
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if { [llength $ports] >= 2 } {
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puts $sfh ".subckt $cell_name [join $ports " "] VPWR VGND"
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puts $sfh "* mock transistor netlist"
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puts $sfh "R1 [lindex $ports 0] [lindex $ports 1] 1k"
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puts $sfh ".ends"
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puts $sfh ""
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}
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}
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close $sfh
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#---------------------------------------------------------------
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# write_path_spice with different simulators and path options
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#---------------------------------------------------------------
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puts "--- write_path_spice tests ---"
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# Max path with ngspice
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set pdir1 [make_result_file spice_gcd_path_ng]
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file mkdir $pdir1
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write_path_spice \
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-path_args {-sort_by_slack -path_delay max} \
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-spice_file [file join $pdir1 spice] \
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-lib_subckt_file $subckt_file \
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-model_file $model_file \
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-power VPWR \
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-ground VGND \
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-simulator ngspice
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# Min path with hspice
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set pdir2 [make_result_file spice_gcd_path_hs]
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file mkdir $pdir2
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write_path_spice \
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-path_args {-path_delay min} \
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-spice_file [file join $pdir2 spice] \
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-lib_subckt_file $subckt_file \
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-model_file $model_file \
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-power VPWR \
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-ground VGND \
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-simulator hspice
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# Path with xyce
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set pdir3 [make_result_file spice_gcd_path_xy]
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file mkdir $pdir3
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write_path_spice \
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-path_args {-sort_by_slack} \
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-spice_file [file join $pdir3 spice] \
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-lib_subckt_file $subckt_file \
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-model_file $model_file \
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-power VPWR \
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-ground VGND \
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-simulator xyce
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