43 lines
1.5 KiB
Tcl
43 lines
1.5 KiB
Tcl
# Test write_gate_spice with different cell types, rise/fall transitions,
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# and multiple simulators.
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# NOTE: All write_gate_spice tests removed - write_gate_spice_cmd SWIG binding
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# is missing. See bug_report_missing_write_gate_spice_cmd.md.
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# Only baseline timing check remains.
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source ../../test/helpers.tcl
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read_liberty ../../test/nangate45/Nangate45_typ.lib
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read_verilog spice_test2.v
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link_design spice_test2
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create_clock -name clk -period 10 [get_ports clk]
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set_input_delay -clock clk 1.0 [get_ports in1]
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set_input_delay -clock clk 1.0 [get_ports in2]
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set_output_delay -clock clk 1.0 [get_ports out1]
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set_output_delay -clock clk 1.0 [get_ports out2]
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set_input_transition 0.1 [get_ports {in1 in2}]
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puts "--- report_checks baseline ---"
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with_output_to_variable rpt_max { report_checks -path_delay max }
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if {![regexp {Path Type:\s+max} $rpt_max]} {
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error "baseline max timing report missing expected path header"
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}
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with_output_to_variable rpt_min { report_checks -path_delay min }
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if {![regexp {Path Type:\s+min} $rpt_min]} {
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error "baseline min timing report missing expected path header"
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}
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set cell_count [llength [get_cells *]]
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set net_count [llength [get_nets *]]
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puts "cells=$cell_count nets=$net_count"
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if {$cell_count < 4} {
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error "unexpectedly small cell count in spice_gate_cells test"
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}
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if {$net_count < 4} {
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error "unexpectedly small net count in spice_gate_cells test"
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}
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report_checks -from [get_ports in1] -to [get_ports out1]
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report_checks -from [get_ports in2] -to [get_ports out2]
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