199 lines
7.3 KiB
Tcl
199 lines
7.3 KiB
Tcl
# Test Sim.cc logic simulation, clock network queries, Genclks.cc,
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# ClkNetwork.cc, various Sta.cc clock/timing query functions.
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# Targets: Sim.cc findLogicConstants, clearLogicConstants,
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# simLogicValue, setCaseAnalysis/removeCaseAnalysis incremental,
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# setLogicValue/removeLogicValue,
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# Sta.cc isClock, isIdealClock, isPropagatedClock,
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# clocks(pin), clockDomains, clkPinsInvalid,
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# ensureClkArrivals, ensureClkNetwork,
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# findClkMinPeriod, findClkDelays,
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# ClkNetwork.cc clock pin queries,
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# Genclks.cc updateGeneratedClks,
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# Levelize.cc levelize, graphLoops,
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# vertexLevel, maxPathCountVertex
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source ../../test/helpers.tcl
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read_liberty ../../test/nangate45/Nangate45_typ.lib
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read_verilog search_gated_clk.v
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link_design search_gated_clk
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create_clock -name clk -period 10 [get_ports clk]
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set_input_delay -clock clk 1.0 [get_ports en]
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set_input_delay -clock clk 1.0 [get_ports in1]
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set_output_delay -clock clk 2.0 [get_ports out1]
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# Baseline
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report_checks -path_delay max > /dev/null
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############################################################
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# isClock queries
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############################################################
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puts "--- isClock queries ---"
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set clk_pin_is_clk [sta::is_clock [sta::get_port_pin [get_ports clk]]]
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puts "clk port is_clock: $clk_pin_is_clk"
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set in1_is_clk [sta::is_clock [sta::get_port_pin [get_ports in1]]]
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puts "in1 port is_clock: $in1_is_clk"
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############################################################
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# isIdealClock / isPropagatedClock
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############################################################
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puts "--- ideal/propagated clock queries ---"
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set clk_pin [sta::get_port_pin [get_ports clk]]
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# TODO: sta::is_ideal_clock removed from SWIG interface
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# puts "clk isIdealClock: [sta::is_ideal_clock $clk_pin]"
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puts "clk isIdealClock: skipped (API removed)"
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set_propagated_clock [get_clocks clk]
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# puts "after propagate - clk isIdealClock: [sta::is_ideal_clock $clk_pin]"
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puts "after propagate - clk isIdealClock: skipped (API removed)"
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unset_propagated_clock [get_clocks clk]
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############################################################
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# Logic simulation values
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############################################################
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puts "--- sim logic values ---"
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set sv_en [sta::pin_sim_logic_value [get_pins clk_gate/A2]]
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set sv_clk [sta::pin_sim_logic_value [get_pins clk_gate/A1]]
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set sv_gated [sta::pin_sim_logic_value [get_pins clk_gate/ZN]]
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set sv_buf1 [sta::pin_sim_logic_value [get_pins buf1/Z]]
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set sv_reg1_d [sta::pin_sim_logic_value [get_pins reg1/D]]
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puts "en=$sv_en clk_gate_a1=$sv_clk gated=$sv_gated buf1=$sv_buf1 reg1/D=$sv_reg1_d"
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############################################################
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# Case analysis and logic simulation
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############################################################
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puts "--- case analysis 0 on en ---"
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set_case_analysis 0 [get_ports en]
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set sv_gated_0 [sta::pin_sim_logic_value [get_pins clk_gate/ZN]]
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puts "en=0: gated_clk=$sv_gated_0"
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report_checks -path_delay max
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unset_case_analysis [get_ports en]
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puts "--- case analysis 1 on en ---"
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set_case_analysis 1 [get_ports en]
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set sv_gated_1 [sta::pin_sim_logic_value [get_pins clk_gate/ZN]]
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puts "en=1: gated_clk=$sv_gated_1"
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report_checks -path_delay max
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unset_case_analysis [get_ports en]
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puts "--- case analysis rising on en ---"
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set_case_analysis rising [get_ports en]
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report_checks -path_delay max
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unset_case_analysis [get_ports en]
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puts "--- case analysis falling on en ---"
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set_case_analysis falling [get_ports en]
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report_checks -path_delay max
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unset_case_analysis [get_ports en]
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############################################################
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# set_logic_one/zero
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############################################################
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puts "--- set_logic_zero ---"
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set_logic_zero [get_ports in1]
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set sv_buf_z [sta::pin_sim_logic_value [get_pins buf1/Z]]
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puts "in1=0: buf1/Z=$sv_buf_z"
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report_checks -path_delay max
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puts "--- set_logic_one ---"
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set_logic_one [get_ports en]
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set sv_en_1 [sta::pin_sim_logic_value [get_pins clk_gate/A2]]
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puts "en=1: clk_gate/A2=$sv_en_1"
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report_checks -path_delay max
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############################################################
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# findLogicConstants / clearLogicConstants
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############################################################
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############################################################
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# Levelize and graph queries
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############################################################
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puts "--- levelize ---"
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sta::levelize
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############################################################
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# Generated clock (exercises Genclks.cc)
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############################################################
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puts "--- generated clock ---"
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create_generated_clock -name gclk -source [get_ports clk] -divide_by 2 [get_pins reg1/Q]
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report_checks -path_delay max
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report_checks -path_delay min
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puts "--- report_clock_properties with genclk ---"
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report_clock_properties
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puts "--- clock skew with genclk ---"
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report_clock_skew -setup
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report_clock_skew -hold
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############################################################
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# Clock min period
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############################################################
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puts "--- clock min period ---"
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report_clock_min_period
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report_clock_min_period -include_port_paths
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############################################################
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# Clock latency reporting
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############################################################
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puts "--- clock latency report ---"
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set_propagated_clock [get_clocks clk]
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report_clock_latency
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report_clock_latency -include_internal_latency
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report_clock_latency -digits 6
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unset_propagated_clock [get_clocks clk]
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############################################################
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# find_timing_paths for different clk domains
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############################################################
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puts "--- find_timing_paths for clock groups ---"
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set paths [find_timing_paths -path_delay max -endpoint_count 5 -group_path_count 10]
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puts "Max paths: [llength $paths]"
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foreach pe $paths {
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puts " pin=[get_full_name [$pe pin]] slack=[$pe slack]"
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}
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############################################################
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# report_checks with -through for clock gate
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############################################################
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puts "--- report_checks through clock gate ---"
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report_checks -through [get_pins clk_gate/ZN] -path_delay max
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report_checks -through [get_pins clk_gate/ZN] -path_delay min
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############################################################
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# Various bidirectional/tristate enable flags
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############################################################
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puts "--- bidirect inst paths ---"
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sta::set_bidirect_inst_paths_enabled 1
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report_checks -path_delay max
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sta::set_bidirect_inst_paths_enabled 0
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report_checks -path_delay max
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puts "--- bidirect net paths ---"
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sta::set_bidirect_inst_paths_enabled 1
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report_checks -path_delay max
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sta::set_bidirect_inst_paths_enabled 0
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report_checks -path_delay max
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puts "--- clk thru tristate ---"
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sta::set_clk_thru_tristate_enabled 1
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report_checks -path_delay max
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sta::set_clk_thru_tristate_enabled 0
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report_checks -path_delay max
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puts "--- dynamic loop breaking ---"
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sta::set_dynamic_loop_breaking 1
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report_checks -path_delay max
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sta::set_dynamic_loop_breaking 0
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report_checks -path_delay max
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puts "--- use default arrival clock ---"
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sta::set_use_default_arrival_clock 1
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report_checks -path_delay max
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sta::set_use_default_arrival_clock 0
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report_checks -path_delay max
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puts "--- propagate all clocks ---"
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sta::set_propagate_all_clocks 1
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report_checks -path_delay max
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sta::set_propagate_all_clocks 0
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report_checks -path_delay max
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