272 lines
9.5 KiB
Tcl
272 lines
9.5 KiB
Tcl
# Test Sim.cc constant propagation, clock gating simulation,
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# Levelize.cc deeper loop/level operations,
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# and Sta.cc constraint-related functions.
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# Targets: Sim.cc setPinValue, evalInstance, clockGateOutValue,
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# annotateGraphEdges, annotateVertexEdges, seedConstants,
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# propagateConstants, setConstraintConstPins, setConstFuncPins,
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# enqueueConstantPinInputs, removePropagatedValue,
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# Levelize.cc levelize, reportLoops, GraphLoop::report,
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# Sta.cc setLogicValue, findLogicConstants, clearLogicConstants,
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# setCaseAnalysis, removeCaseAnalysis, set/unset propagated clock,
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# setClockLatency, removeClockLatency, setClockInsertion,
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# setClockUncertainty, removeClockUncertainty,
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# setLatchBorrowLimit, setMinPulseWidth
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source ../../test/helpers.tcl
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read_liberty ../../test/nangate45/Nangate45_typ.lib
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read_verilog search_data_check_gated.v
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link_design search_data_check_gated
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create_clock -name clk -period 10 [get_ports clk]
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set_input_delay -clock clk 1.0 [get_ports en]
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set_input_delay -clock clk 1.0 [get_ports in1]
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set_input_delay -clock clk 1.0 [get_ports in2]
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set_input_delay -clock clk 0.5 [get_ports rst]
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set_output_delay -clock clk 2.0 [get_ports out1]
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set_output_delay -clock clk 2.0 [get_ports out2]
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set_output_delay -clock clk 2.0 [get_ports out3]
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report_checks > /dev/null
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############################################################
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# set_logic_zero on multiple pins
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############################################################
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puts "--- set_logic_zero in1 ---"
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set_logic_zero [get_ports in1]
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set sv [sta::pin_sim_logic_value [get_pins and1/A1]]
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puts "in1=0 and1/A1=$sv"
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report_checks -path_delay max
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puts "--- set_logic_zero in2 ---"
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set_logic_zero [get_ports in2]
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set sv2 [sta::pin_sim_logic_value [get_pins and1/A2]]
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puts "in2=0 and1/A2=$sv2"
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set sv_zn [sta::pin_sim_logic_value [get_pins and1/ZN]]
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puts "and1/ZN=$sv_zn"
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report_checks -path_delay max
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############################################################
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# set_logic_one
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############################################################
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puts "--- set_logic_one en ---"
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set_logic_one [get_ports en]
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set sv_en [sta::pin_sim_logic_value [get_pins clk_gate/A2]]
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puts "en=1: clk_gate/A2=$sv_en"
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set sv_gated [sta::pin_sim_logic_value [get_pins clk_gate/ZN]]
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puts "gated_clk=$sv_gated"
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report_checks -path_delay max
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############################################################
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# set_logic_one in1 (overwrite zero)
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############################################################
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puts "--- set_logic_one in1 (overwrite) ---"
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set_logic_one [get_ports in1]
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set sv_a1 [sta::pin_sim_logic_value [get_pins and1/A1]]
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puts "in1=1 and1/A1=$sv_a1"
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set sv_zn2 [sta::pin_sim_logic_value [get_pins and1/ZN]]
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puts "and1/ZN=$sv_zn2 (in1=1,in2=0 -> 0)"
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report_checks -path_delay max
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############################################################
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# Case analysis with rising/falling
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############################################################
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puts "--- case_analysis 0 on en ---"
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set_case_analysis 0 [get_ports en]
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set sv_gated_0 [sta::pin_sim_logic_value [get_pins clk_gate/ZN]]
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puts "en=0: gated_clk=$sv_gated_0"
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report_checks -path_delay max
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unset_case_analysis [get_ports en]
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puts "--- case_analysis 1 on en ---"
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set_case_analysis 1 [get_ports en]
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set sv_gated_1 [sta::pin_sim_logic_value [get_pins clk_gate/ZN]]
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puts "en=1: gated_clk=$sv_gated_1"
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report_checks -path_delay max
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unset_case_analysis [get_ports en]
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puts "--- case_analysis rising on rst ---"
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set_case_analysis rising [get_ports rst]
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report_checks -path_delay max
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unset_case_analysis [get_ports rst]
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puts "--- case_analysis falling on rst ---"
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set_case_analysis falling [get_ports rst]
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report_checks -path_delay max
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unset_case_analysis [get_ports rst]
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############################################################
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# Constants are handled via case_analysis and logic_one/zero
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# which drive Sim.cc propagation internally
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############################################################
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puts "--- Constant propagation via case_analysis ---"
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set_case_analysis 0 [get_ports in1]
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set_case_analysis 0 [get_ports in2]
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set sv_zn3 [sta::pin_sim_logic_value [get_pins and1/ZN]]
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puts "in1=0,in2=0: and1/ZN=$sv_zn3"
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set sv_inv [sta::pin_sim_logic_value [get_pins inv1/ZN]]
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puts "inv1/ZN=$sv_inv"
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report_checks -path_delay max
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unset_case_analysis [get_ports in1]
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unset_case_analysis [get_ports in2]
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############################################################
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# Levelize operations
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############################################################
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puts "--- levelize ---"
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sta::levelize
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puts "--- report_loops ---"
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sta::report_loops
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############################################################
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# Clock constraints
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############################################################
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puts "--- set_propagated_clock ---"
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set_propagated_clock [get_clocks clk]
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report_checks -path_delay max
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puts "--- report_clock_skew after propagation ---"
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report_clock_skew -setup
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report_clock_skew -hold
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puts "--- unset_propagated_clock ---"
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unset_propagated_clock [get_clocks clk]
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############################################################
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# Clock latency
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############################################################
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puts "--- set_clock_latency -source ---"
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set_clock_latency -source 0.2 [get_clocks clk]
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report_checks -path_delay max
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puts "--- set_clock_latency (network) ---"
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set_clock_latency 0.1 [get_clocks clk]
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report_checks -path_delay max
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puts "--- unset_clock_latency ---"
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unset_clock_latency [get_clocks clk]
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unset_clock_latency -source [get_clocks clk]
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############################################################
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# Clock insertion delay
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############################################################
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puts "--- set_clock_latency -source -rise ---"
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set_clock_latency -source -rise 0.15 [get_clocks clk]
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report_checks -path_delay max
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puts "--- set_clock_latency -source -fall ---"
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set_clock_latency -source -fall 0.2 [get_clocks clk]
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report_checks -path_delay max
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puts "--- unset ---"
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unset_clock_latency -source [get_clocks clk]
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############################################################
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# Clock uncertainty
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############################################################
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puts "--- set_clock_uncertainty ---"
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set_clock_uncertainty 0.5 [get_clocks clk]
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report_checks -path_delay max
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puts "--- set_clock_uncertainty -setup ---"
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set_clock_uncertainty -setup 0.3 [get_clocks clk]
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report_checks -path_delay max
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puts "--- set_clock_uncertainty -hold ---"
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set_clock_uncertainty -hold 0.2 [get_clocks clk]
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report_checks -path_delay min
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puts "--- unset_clock_uncertainty ---"
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unset_clock_uncertainty [get_clocks clk]
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############################################################
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# Latch borrow limit
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############################################################
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puts "--- set_max_time_borrow ---"
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set_max_time_borrow 1.0 [get_clocks clk]
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report_checks -path_delay max
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############################################################
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# Min pulse width
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############################################################
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report_check_types -min_pulse_width
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############################################################
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# report_constant
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############################################################
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puts "--- report_constant ---"
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set_case_analysis 0 [get_ports in1]
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report_constant [get_ports in1]
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report_constant [get_cells and1]
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unset_case_analysis [get_ports in1]
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############################################################
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# Disable timing on various targets
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############################################################
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puts "--- set_disable_timing port ---"
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set_disable_timing [get_ports in1]
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report_checks -path_delay max
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unset_disable_timing [get_ports in1]
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puts "--- set_disable_timing instance ---"
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set_disable_timing [get_cells buf1]
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report_checks -path_delay max
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unset_disable_timing [get_cells buf1]
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report_checks -path_delay max
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############################################################
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# CRPR settings
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############################################################
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puts "--- CRPR settings ---"
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sta::set_crpr_enabled 1
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puts "crpr_enabled: [sta::crpr_enabled]"
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sta::set_crpr_mode "same_pin"
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puts "crpr_mode: [sta::crpr_mode]"
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report_checks -path_delay max
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sta::set_crpr_mode "same_transition"
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puts "crpr_mode: [sta::crpr_mode]"
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report_checks -path_delay max
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sta::set_crpr_enabled 0
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############################################################
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# Recovery/removal checks
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############################################################
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puts "--- recovery/removal checks ---"
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sta::set_recovery_removal_checks_enabled 1
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report_checks -path_delay max
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sta::set_recovery_removal_checks_enabled 0
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############################################################
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# Gated clock checks
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############################################################
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puts "--- gated clock checks ---"
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sta::set_gated_clk_checks_enabled 1
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sta::set_propagate_gated_clock_enable 1
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report_checks -path_delay max
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sta::set_gated_clk_checks_enabled 0
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sta::set_propagate_gated_clock_enable 0
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############################################################
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# Timing derate
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############################################################
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puts "--- timing_derate ---"
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set_timing_derate -early 0.95
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set_timing_derate -late 1.05
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report_checks -path_delay max
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report_checks -path_delay min
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unset_timing_derate
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############################################################
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# Tag/group reporting (for Tag.cc coverage)
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############################################################
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puts "--- tag/group reporting ---"
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puts "tag_count: [sta::tag_count]"
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puts "tag_group_count: [sta::tag_group_count]"
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puts "clk_info_count: [sta::clk_info_count]"
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puts "path_count: [sta::path_count]"
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puts "--- report internal ---"
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sta::report_tags
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sta::report_clk_infos
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sta::report_tag_groups
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