280 lines
12 KiB
Tcl
280 lines
12 KiB
Tcl
# Test Property.cc deeper: more property queries, PathEnd properties,
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# Clock generated properties, net_slack, endpoint properties,
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# pin arrival/required/slack variants, edge properties deep.
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# Also test report_path format variants and field customization.
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# Targets: Property.cc getProperty for PathEnd, Path, Edge, Clock (gen),
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# TimingArcSet properties, resistancePropertyValue,
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# capacitancePropertyValue, Port properties deeper,
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# ReportPath.cc reportPath, reportPathFull, reportPath3,
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# setReportFieldOrder, setReportPathFields, reportGenClkSrcAndPath,
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# reportJson, reportShort(PathEndUnconstrained)
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source ../../test/helpers.tcl
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read_liberty ../../test/nangate45/Nangate45_typ.lib
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read_verilog search_genclk.v
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link_design search_genclk
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create_clock -name clk -period 10 [get_ports clk]
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create_generated_clock -name div_clk -source [get_pins clkbuf/Z] -divide_by 2 [get_pins div_reg/Q]
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set_input_delay -clock clk 1.0 [get_ports in1]
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set_input_delay -clock clk 1.0 [get_ports in2]
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set_output_delay -clock clk 2.0 [get_ports out1]
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set_output_delay -clock div_clk 1.0 [get_ports out2]
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# Run timing
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report_checks -path_delay max > /dev/null
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############################################################
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# Generated clock properties
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############################################################
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puts "--- Generated clock properties ---"
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set gclk [get_clocks div_clk]
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puts "gen clock name: [get_property $gclk name]"
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puts "gen clock period: [get_property $gclk period]"
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puts "gen clock is_generated: [get_property $gclk is_generated]"
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puts "gen clock is_virtual: [get_property $gclk is_virtual]"
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set gsrc [get_property $gclk sources]
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puts "gen clock sources: [llength $gsrc]"
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############################################################
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# Pin properties on clock pins
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############################################################
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puts "--- Clock pin properties ---"
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set ck_pin [get_pins div_reg/CK]
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puts "div_reg/CK is_clock: [get_property $ck_pin is_clock]"
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puts "div_reg/CK is_register_clock: [get_property $ck_pin is_register_clock]"
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set cks [get_property $ck_pin clocks]
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puts "div_reg/CK clocks: [llength $cks]"
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set cdoms [get_property $ck_pin clock_domains]
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puts "div_reg/CK clock_domains: [llength $cdoms]"
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############################################################
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# Pin timing properties - arrival, slew, slack variants
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############################################################
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puts "--- Pin timing properties deep ---"
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set dpin [get_pins reg1/D]
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puts "arrival_max_rise: [get_property $dpin arrival_max_rise]"
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puts "arrival_max_fall: [get_property $dpin arrival_max_fall]"
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puts "arrival_min_rise: [get_property $dpin arrival_min_rise]"
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puts "arrival_min_fall: [get_property $dpin arrival_min_fall]"
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puts "slack_max: [get_property $dpin slack_max]"
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puts "slack_max_rise: [get_property $dpin slack_max_rise]"
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puts "slack_max_fall: [get_property $dpin slack_max_fall]"
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puts "slack_min: [get_property $dpin slack_min]"
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puts "slack_min_rise: [get_property $dpin slack_min_rise]"
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puts "slack_min_fall: [get_property $dpin slack_min_fall]"
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puts "slew_max: [get_property $dpin slew_max]"
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puts "slew_max_rise: [get_property $dpin slew_max_rise]"
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puts "slew_max_fall: [get_property $dpin slew_max_fall]"
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puts "slew_min: [get_property $dpin slew_min]"
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puts "slew_min_rise: [get_property $dpin slew_min_rise]"
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puts "slew_min_fall: [get_property $dpin slew_min_fall]"
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############################################################
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# Port properties
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############################################################
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puts "--- Port properties deep ---"
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set in_port [get_ports in1]
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puts "port name: [get_property $in_port name]"
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puts "port direction: [get_property $in_port direction]"
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set out_port [get_ports out1]
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puts "out port direction: [get_property $out_port direction]"
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set clk_port [get_ports clk]
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puts "clk port direction: [get_property $clk_port direction]"
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############################################################
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# Net properties
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############################################################
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puts "--- Net properties ---"
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set net1 [get_nets n1]
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puts "net name: [get_property $net1 name]"
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puts "net full_name: [get_property $net1 full_name]"
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############################################################
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# Instance properties
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############################################################
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puts "--- Instance properties deep ---"
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set inst1 [get_cells reg1]
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puts "inst name: [get_property $inst1 name]"
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puts "inst full_name: [get_property $inst1 full_name]"
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puts "inst ref_name: [get_property $inst1 ref_name]"
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set icell [get_property $inst1 cell]
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puts "inst cell: [get_name $icell]"
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############################################################
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# LibertyCell properties
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############################################################
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puts "--- LibertyCell properties ---"
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set lc [get_lib_cells NangateOpenCellLibrary/AND2_X1]
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puts "lib_cell name: [get_property $lc name]"
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puts "lib_cell full_name: [get_property $lc full_name]"
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puts "lib_cell base_name: [get_property $lc base_name]"
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puts "lib_cell filename: [get_property $lc filename]"
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puts "lib_cell is_buffer: [get_property $lc is_buffer]"
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set lib_ref [get_property $lc library]
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puts "lib_cell library: [get_name $lib_ref]"
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############################################################
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# LibertyPort properties
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############################################################
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puts "--- LibertyPort properties ---"
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set lp [get_lib_pins NangateOpenCellLibrary/AND2_X1/ZN]
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puts "lib_port name: [get_property $lp name]"
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puts "lib_port full_name: [get_property $lp full_name]"
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puts "lib_port direction: [get_property $lp direction]"
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############################################################
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# Library properties
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############################################################
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puts "--- Library properties ---"
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set lib [get_libs NangateOpenCellLibrary]
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puts "lib name: [get_property $lib name]"
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puts "lib full_name: [get_property $lib full_name]"
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############################################################
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# Edge properties with timing arc details
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############################################################
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puts "--- Edge properties deep ---"
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set edges [get_timing_edges -from [get_pins and1/A1] -to [get_pins and1/ZN]]
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foreach edge $edges {
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puts "edge full_name: [get_property $edge full_name]"
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puts "edge delay_min_fall: [get_property $edge delay_min_fall]"
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puts "edge delay_max_fall: [get_property $edge delay_max_fall]"
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puts "edge delay_min_rise: [get_property $edge delay_min_rise]"
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puts "edge delay_max_rise: [get_property $edge delay_max_rise]"
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puts "edge sense: [get_property $edge sense]"
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set efp [get_property $edge from_pin]
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puts "edge from_pin: [get_full_name $efp]"
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set etp [get_property $edge to_pin]
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puts "edge to_pin: [get_full_name $etp]"
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break
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}
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############################################################
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# PathEnd properties deep
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############################################################
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puts "--- PathEnd properties deep ---"
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set paths [find_timing_paths -path_delay max -endpoint_count 5]
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foreach pe $paths {
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set sp [get_property $pe startpoint]
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puts "startpoint: [get_full_name $sp]"
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set ep [get_property $pe endpoint]
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puts "endpoint: [get_full_name $ep]"
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puts "slack: [get_property $pe slack]"
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set sc [get_property $pe startpoint_clock]
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puts "startpoint_clock: [get_name $sc]"
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set ec [get_property $pe endpoint_clock]
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puts "endpoint_clock: [get_name $ec]"
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if { [$pe is_check] } {
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set ecp [get_property $pe endpoint_clock_pin]
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puts "endpoint_clock_pin: [get_full_name $ecp]"
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}
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# PathEnd methods
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puts " is_check: [$pe is_check]"
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puts " is_output_delay: [$pe is_output_delay]"
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puts " is_unconstrained: [$pe is_unconstrained]"
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puts " is_path_delay: [$pe is_path_delay]"
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puts " is_latch_check: [$pe is_latch_check]"
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puts " is_data_check: [$pe is_data_check]"
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puts " is_gated_clock: [$pe is_gated_clock]"
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puts " margin: [$pe margin]"
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puts " data_required_time: [$pe data_required_time]"
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puts " data_arrival_time: [$pe data_arrival_time]"
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puts " source_clk_latency: [$pe source_clk_latency]"
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puts " target_clk: [get_name [$pe target_clk]]"
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puts " target_clk_delay: [$pe target_clk_delay]"
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puts " clk_skew: [$pe clk_skew]"
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puts " min_max: [$pe min_max]"
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puts " end_transition: [$pe end_transition]"
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puts " check_role: [$pe check_role]"
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break
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}
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############################################################
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# Path properties
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############################################################
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puts "--- Path properties deep ---"
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foreach pe $paths {
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set p [$pe path]
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puts "path pin: [get_full_name [$p pin]]"
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puts "path arrival: [$p arrival]"
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puts "path required: [$p required]"
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puts "path slack: [$p slack]"
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puts "path edge: [$p edge]"
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set ppins [$p pins]
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puts "path pins count: [llength $ppins]"
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break
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}
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############################################################
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# Report checks in all format variants
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############################################################
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puts "--- report_checks -format full ---"
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report_checks -path_delay max -format full
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puts "--- report_checks -format full_clock ---"
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report_checks -path_delay max -format full_clock
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puts "--- report_checks -format full_clock_expanded ---"
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report_checks -path_delay max -format full_clock_expanded
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puts "--- report_checks -format short ---"
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report_checks -path_delay max -format short
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puts "--- report_checks -format end ---"
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report_checks -path_delay max -format end
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puts "--- report_checks -format slack_only ---"
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report_checks -path_delay max -format slack_only
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puts "--- report_checks -format summary ---"
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report_checks -path_delay max -format summary
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puts "--- report_checks -format json ---"
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report_checks -path_delay max -format json
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############################################################
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# Report checks with different -fields
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############################################################
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puts "--- report_checks with -fields combinations ---"
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report_checks -path_delay max -fields {capacitance slew fanout}
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report_checks -path_delay max -fields {input_pin net}
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report_checks -path_delay max -fields {capacitance slew fanout input_pin net src_attr}
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############################################################
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# report_checks with -digits
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############################################################
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puts "--- report_checks -digits 6 ---"
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report_checks -path_delay max -digits 6
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############################################################
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# report_checks -no_line_splits
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############################################################
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puts "--- report_checks -no_line_splits ---"
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report_checks -path_delay max -no_line_splits
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############################################################
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# report_checks to generated clock domain
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############################################################
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puts "--- report_checks to div_clk domain ---"
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report_checks -to [get_ports out2] -format full_clock_expanded
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############################################################
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# report_checks -unconstrained
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############################################################
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puts "--- report_checks -unconstrained ---"
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report_checks -path_delay max -unconstrained
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############################################################
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# get_property -object_type
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############################################################
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puts "--- get_property -object_type ---"
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puts "inst: [get_property -object_type instance reg1 name]"
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puts "pin: [get_property -object_type pin reg1/D name]"
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puts "net: [get_property -object_type net n1 name]"
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puts "port: [get_property -object_type port in1 name]"
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puts "clock: [get_property -object_type clock clk name]"
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puts "lib_cell: [get_property -object_type liberty_cell NangateOpenCellLibrary/AND2_X1 name]"
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puts "lib_pin: [get_property -object_type liberty_port NangateOpenCellLibrary/AND2_X1/ZN name]"
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puts "library: [get_property -object_type library NangateOpenCellLibrary name]"
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