458 lines
17 KiB
Plaintext
458 lines
17 KiB
Plaintext
=== SLEW LIMIT CHECKS ===
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--- set_max_transition tight limit ---
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max slew
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Pin reg1/QN v
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max slew 0.00
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slew 0.01
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----------------
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Slack -0.01 (VIOLATED)
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--- report_check_types -max_slew only ---
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max slew
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Pin Limit Slew Slack
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------------------------------------------------------------
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reg1/QN 0.00 0.01 -0.01 (VIOLATED)
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--- report_check_types -max_slew -violators ---
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max slew
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Pin Limit Slew Slack
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------------------------------------------------------------
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reg1/QN 0.00 0.01 -0.01 (VIOLATED)
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reg2/QN 0.00 0.01 -0.01 (VIOLATED)
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reg3/QN 0.00 0.01 -0.01 (VIOLATED)
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buf3/A 0.00 0.01 -0.01 (VIOLATED)
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buf4/A 0.00 0.01 -0.01 (VIOLATED)
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buf5/A 0.00 0.01 -0.01 (VIOLATED)
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inv2/ZN 0.00 0.01 -0.01 (VIOLATED)
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and2/A2 0.00 0.01 -0.01 (VIOLATED)
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or1/ZN 0.00 0.01 -0.01 (VIOLATED)
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buf6/A 0.00 0.01 -0.01 (VIOLATED)
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reg1/Q 0.00 0.01 -0.01 (VIOLATED)
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buf1/Z 0.00 0.01 -0.01 (VIOLATED)
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inv1/A 0.00 0.01 -0.01 (VIOLATED)
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buf2/Z 0.00 0.01 -0.01 (VIOLATED)
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inv2/A 0.00 0.01 -0.01 (VIOLATED)
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and2/ZN 0.00 0.01 -0.01 (VIOLATED)
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buf1/A 0.00 0.01 -0.01 (VIOLATED)
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and1/ZN 0.00 0.01 -0.01 (VIOLATED)
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and2/A1 0.00 0.01 -0.01 (VIOLATED)
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buf3/Z 0.00 0.01 -0.00 (VIOLATED)
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buf4/Z 0.00 0.01 -0.00 (VIOLATED)
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buf5/Z 0.00 0.01 -0.00 (VIOLATED)
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reg1/D 0.00 0.01 -0.00 (VIOLATED)
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reg2/D 0.00 0.01 -0.00 (VIOLATED)
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reg3/D 0.00 0.01 -0.00 (VIOLATED)
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out2 0.00 0.01 -0.00 (VIOLATED)
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out3 0.00 0.01 -0.00 (VIOLATED)
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reg2/Q 0.00 0.01 -0.00 (VIOLATED)
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reg3/Q 0.00 0.01 -0.00 (VIOLATED)
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buf2/A 0.00 0.00 -0.00 (VIOLATED)
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inv1/ZN 0.00 0.00 -0.00 (VIOLATED)
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out1 0.00 0.00 -0.00 (VIOLATED)
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buf6/Z 0.00 0.00 -0.00 (VIOLATED)
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--- set_max_transition on clock ---
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max slew
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Pin reg1/QN v
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max slew 0.00
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slew 0.01
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----------------
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Slack -0.01 (VIOLATED)
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--- set_max_transition on port ---
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max slew
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Pin reg1/QN v
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max slew 0.00
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slew 0.01
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----------------
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Slack -0.01 (VIOLATED)
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=== CAPACITANCE LIMIT CHECKS ===
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--- set_max_capacitance tight limit ---
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max capacitance
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Pin inv2/ZN ^
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max capacitance 0.00
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capacitance 2.92
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-----------------------
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Slack -2.92 (VIOLATED)
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--- report_check_types -max_capacitance only ---
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max capacitance
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Pin Limit Cap Slack
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------------------------------------------------------------
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inv2/ZN 0.00 2.92 -2.92 (VIOLATED)
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--- report_check_types -max_capacitance -violators ---
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max capacitance
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Pin Limit Cap Slack
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------------------------------------------------------------
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inv2/ZN 0.00 2.92 -2.92 (VIOLATED)
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buf1/Z 0.00 1.70 -1.70 (VIOLATED)
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buf2/Z 0.00 1.70 -1.70 (VIOLATED)
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buf3/Z 0.00 1.14 -1.14 (VIOLATED)
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buf4/Z 0.00 1.14 -1.14 (VIOLATED)
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buf5/Z 0.00 1.14 -1.14 (VIOLATED)
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--- set_max_capacitance on port ---
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max capacitance
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Pin inv2/ZN ^
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max capacitance 0.00
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capacitance 2.92
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-----------------------
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Slack -2.92 (VIOLATED)
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=== FANOUT LIMIT CHECKS ===
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--- set_max_fanout tight limit ---
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max fanout
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Pin inv2/ZN
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max fanout 1
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fanout 3
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-----------------
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Slack -2 (VIOLATED)
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--- report_check_types -max_fanout only ---
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max fanout
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Pin Limit Fanout Slack
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---------------------------------------------------------
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inv2/ZN 1 3 -2 (VIOLATED)
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--- report_check_types -max_fanout -violators ---
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max fanout
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Pin Limit Fanout Slack
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---------------------------------------------------------
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inv2/ZN 1 3 -2 (VIOLATED)
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--- set_max_fanout on port ---
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max fanout
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Pin inv2/ZN
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max fanout 1
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fanout 3
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-----------------
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Slack -2 (VIOLATED)
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=== PULSE WIDTH CHECKS ===
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--- report_min_pulse_width_checks ---
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Required Actual
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Pin Width Width Slack
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------------------------------------------------------------
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reg1/CK (high) 0.05 5.00 4.95 (MET)
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--- report_min_pulse_width_checks -verbose ---
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Pin: reg1/CK
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Check: sequential_clock_pulse_width
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 reg1/CK
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0.00 open edge arrival time
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5.00 5.00 clock clk (fall edge)
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0.00 5.00 clock network delay (ideal)
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0.00 5.00 reg1/CK
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0.00 5.00 clock reconvergence pessimism
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5.00 close edge arrival time
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---------------------------------------------------------
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0.05 required pulse width (high)
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5.00 actual pulse width
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---------------------------------------------------------
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4.95 slack (MET)
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--- report_min_pulse_width_checks on specific pin ---
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report_min_pulse_width_checks pin: skipped (API removed)
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--- set_min_pulse_width ---
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Pin: reg1/CK
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Check: sequential_clock_pulse_width
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 reg1/CK
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0.00 open edge arrival time
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5.00 5.00 clock clk (fall edge)
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0.00 5.00 clock network delay (ideal)
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0.00 5.00 reg1/CK
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0.00 5.00 clock reconvergence pessimism
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5.00 close edge arrival time
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---------------------------------------------------------
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5.00 required pulse width (high)
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5.00 actual pulse width
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---------------------------------------------------------
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0.00 slack (MET)
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report_min_pulse_width_checks pin: skipped (API removed)
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Pin: reg2/CK
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Check: sequential_clock_pulse_width
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 reg2/CK
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0.00 open edge arrival time
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5.00 5.00 clock clk (fall edge)
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0.00 5.00 clock network delay (ideal)
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0.00 5.00 reg2/CK
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0.00 5.00 clock reconvergence pessimism
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5.00 close edge arrival time
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---------------------------------------------------------
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5.00 required pulse width (high)
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5.00 actual pulse width
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---------------------------------------------------------
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0.00 slack (MET)
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--- report_check_types -min_pulse_width ---
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Required Actual
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Pin Width Width Slack
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------------------------------------------------------------
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reg2/CK (high) 5.00 5.00 0.00 (MET)
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Pin: reg2/CK
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Check: sequential_clock_pulse_width
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 reg2/CK
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0.00 open edge arrival time
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5.00 5.00 clock clk (fall edge)
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0.00 5.00 clock network delay (ideal)
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0.00 5.00 reg2/CK
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0.00 5.00 clock reconvergence pessimism
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5.00 close edge arrival time
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---------------------------------------------------------
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5.00 required pulse width (high)
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5.00 actual pulse width
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---------------------------------------------------------
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0.00 slack (MET)
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=== MIN PERIOD CHECKS ===
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--- report_clock_min_period ---
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clk period_min = 0.00 fmax = inf
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--- report_clock_min_period -include_port_paths ---
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clk period_min = 2.10 fmax = 476.13
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--- report_clock_min_period -clocks ---
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clk period_min = 0.00 fmax = inf
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--- Tight clock period for min_period violations ---
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--- report_clock_min_period with violation ---
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clk period_min = 0.00 fmax = inf
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=== MAX SKEW CHECKS ===
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--- report_check_types -max_skew ---
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=== COMBINED CHECKS ===
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--- report_check_types -violators (all) ---
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Group Slack
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--------------------------------------------
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clk -2.09
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clk -2.07
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clk -2.07
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clk -1.19
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clk -1.19
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clk -1.19
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max slew
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Pin Limit Slew Slack
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------------------------------------------------------------
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reg1/QN 0.00 0.01 -0.01 (VIOLATED)
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reg2/QN 0.00 0.01 -0.01 (VIOLATED)
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reg3/QN 0.00 0.01 -0.01 (VIOLATED)
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buf3/A 0.00 0.01 -0.01 (VIOLATED)
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buf4/A 0.00 0.01 -0.01 (VIOLATED)
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buf5/A 0.00 0.01 -0.01 (VIOLATED)
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inv2/ZN 0.00 0.01 -0.01 (VIOLATED)
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and2/A2 0.00 0.01 -0.01 (VIOLATED)
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or1/ZN 0.00 0.01 -0.01 (VIOLATED)
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buf6/A 0.00 0.01 -0.01 (VIOLATED)
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reg1/Q 0.00 0.01 -0.01 (VIOLATED)
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buf1/Z 0.00 0.01 -0.01 (VIOLATED)
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inv1/A 0.00 0.01 -0.01 (VIOLATED)
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buf2/Z 0.00 0.01 -0.01 (VIOLATED)
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inv2/A 0.00 0.01 -0.01 (VIOLATED)
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and2/ZN 0.00 0.01 -0.01 (VIOLATED)
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buf1/A 0.00 0.01 -0.01 (VIOLATED)
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and1/ZN 0.00 0.01 -0.01 (VIOLATED)
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and2/A1 0.00 0.01 -0.01 (VIOLATED)
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buf3/Z 0.00 0.01 -0.00 (VIOLATED)
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buf4/Z 0.00 0.01 -0.00 (VIOLATED)
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buf5/Z 0.00 0.01 -0.00 (VIOLATED)
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reg1/D 0.00 0.01 -0.00 (VIOLATED)
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reg2/D 0.00 0.01 -0.00 (VIOLATED)
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reg3/D 0.00 0.01 -0.00 (VIOLATED)
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out2 0.00 0.01 -0.00 (VIOLATED)
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out3 0.00 0.01 -0.00 (VIOLATED)
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reg2/Q 0.00 0.01 -0.00 (VIOLATED)
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reg3/Q 0.00 0.01 -0.00 (VIOLATED)
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buf2/A 0.00 0.00 -0.00 (VIOLATED)
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inv1/ZN 0.00 0.00 -0.00 (VIOLATED)
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out1 0.00 0.00 -0.00 (VIOLATED)
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buf6/Z 0.00 0.00 -0.00 (VIOLATED)
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max fanout
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Pin Limit Fanout Slack
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---------------------------------------------------------
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inv2/ZN 1 3 -2 (VIOLATED)
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max capacitance
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Pin Limit Cap Slack
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------------------------------------------------------------
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inv2/ZN 0.00 2.92 -2.92 (VIOLATED)
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buf1/Z 0.00 1.70 -1.70 (VIOLATED)
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buf2/Z 0.00 1.70 -1.70 (VIOLATED)
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buf3/Z 0.00 1.14 -1.14 (VIOLATED)
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buf4/Z 0.00 1.14 -1.14 (VIOLATED)
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buf5/Z 0.00 1.14 -1.14 (VIOLATED)
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Required Actual
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Pin Width Width Slack
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------------------------------------------------------------
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reg2/CK (high) 5.00 0.01 -4.99 (VIOLATED)
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reg2/CK (low) 5.00 0.01 -4.99 (VIOLATED)
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reg3/CK (high) 5.00 0.01 -4.99 (VIOLATED)
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reg3/CK (low) 5.00 0.01 -4.99 (VIOLATED)
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reg1/CK (high) 4.00 0.01 -3.99 (VIOLATED)
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reg1/CK (low) 0.05 0.01 -0.05 (VIOLATED)
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--- report_check_types verbose (all) ---
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Startpoint: in3 (input port clocked by clk)
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Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: min
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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1.00 1.00 ^ input external delay
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0.00 1.00 ^ in3 (in)
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0.02 1.02 ^ or1/ZN (OR2_X1)
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0.03 1.04 ^ and2/ZN (AND2_X1)
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0.02 1.07 ^ buf1/Z (BUF_X1)
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0.01 1.07 v inv1/ZN (INV_X1)
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0.02 1.10 v buf2/Z (BUF_X1)
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0.01 1.11 ^ inv2/ZN (INV_X1)
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0.02 1.13 ^ buf3/Z (BUF_X1)
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0.00 1.13 ^ reg1/D (DFF_X1)
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1.13 data arrival time
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 clock reconvergence pessimism
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0.00 ^ reg1/CK (DFF_X1)
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0.00 0.00 library hold time
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0.00 data required time
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---------------------------------------------------------
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0.00 data required time
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-1.13 data arrival time
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---------------------------------------------------------
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1.12 slack (MET)
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Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
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Endpoint: out1 (output port clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 ^ reg1/CK (DFF_X1)
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0.08 0.08 ^ reg1/Q (DFF_X1)
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0.02 0.10 ^ buf6/Z (BUF_X1)
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0.00 0.10 ^ out1 (out)
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0.10 data arrival time
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0.01 0.01 clock clk (rise edge)
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0.00 0.01 clock network delay (ideal)
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0.00 0.01 clock reconvergence pessimism
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-2.00 -1.99 output external delay
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-1.99 data required time
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---------------------------------------------------------
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-1.99 data required time
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-0.10 data arrival time
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---------------------------------------------------------
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-2.09 slack (VIOLATED)
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max slew
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Pin reg1/QN v
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max slew 0.00
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slew 0.01
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----------------
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Slack -0.01 (VIOLATED)
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max fanout
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Pin inv2/ZN
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max fanout 1
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fanout 3
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-----------------
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Slack -2 (VIOLATED)
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max capacitance
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Pin inv2/ZN ^
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max capacitance 0.00
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capacitance 2.92
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-----------------------
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Slack -2.92 (VIOLATED)
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Pin: reg2/CK
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Check: sequential_clock_pulse_width
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 reg2/CK
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0.00 open edge arrival time
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0.01 0.01 clock clk (fall edge)
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0.00 0.01 clock network delay (ideal)
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0.00 0.01 reg2/CK
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0.00 0.01 clock reconvergence pessimism
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0.01 close edge arrival time
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---------------------------------------------------------
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5.00 required pulse width (high)
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0.01 actual pulse width
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---------------------------------------------------------
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-4.99 slack (VIOLATED)
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