119 lines
4.3 KiB
Tcl
119 lines
4.3 KiB
Tcl
# Test latch timing paths, time borrowing, latch checks in ReportPath.
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# Targets: ReportPath.cc reportShort/reportFull/reportEndpoint for
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# PathEndLatchCheck, reportBorrowing, latchDesc.
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# Latches.cc, PathEnd.cc PathEndLatchCheck
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source ../../test/helpers.tcl
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read_liberty ../../test/nangate45/Nangate45_typ.lib
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read_verilog search_latch.v
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link_design search_latch
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create_clock -name clk -period 10 [get_ports clk]
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set_input_delay -clock clk 1.0 [get_ports in1]
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set_input_delay -clock clk 1.0 [get_ports in2]
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set_output_delay -clock clk 2.0 [get_ports out1]
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set_output_delay -clock clk 2.0 [get_ports out2]
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puts "--- Latch timing max ---"
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report_checks -path_delay max
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puts "--- Latch timing min ---"
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report_checks -path_delay min
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puts "--- report_checks to latch output ---"
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report_checks -to [get_ports out1] -path_delay max -format full_clock_expanded
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report_checks -to [get_ports out1] -path_delay min -format full_clock_expanded
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puts "--- report_checks to reg output ---"
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report_checks -to [get_ports out2] -path_delay max -format full_clock_expanded
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report_checks -to [get_ports out2] -path_delay min -format full_clock_expanded
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puts "--- report_checks format full_clock ---"
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report_checks -path_delay max -format full_clock
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report_checks -path_delay min -format full_clock
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puts "--- report_checks format short ---"
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report_checks -path_delay max -format short
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report_checks -path_delay min -format short
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puts "--- report_checks format end ---"
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report_checks -path_delay max -format end
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report_checks -path_delay min -format end
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puts "--- report_checks format summary ---"
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report_checks -path_delay max -format summary
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report_checks -path_delay min -format summary
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puts "--- report_checks format json ---"
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report_checks -path_delay max -format json
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report_checks -path_delay min -format json
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puts "--- report_checks format slack_only ---"
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report_checks -path_delay max -format slack_only
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report_checks -path_delay min -format slack_only
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puts "--- find_timing_paths latch check ---"
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set paths [find_timing_paths -path_delay max -endpoint_count 10 -group_path_count 20]
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puts "Found [llength $paths] max paths"
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foreach pe $paths {
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puts " is_latch_check: [$pe is_latch_check] is_check: [$pe is_check] pin=[get_full_name [$pe pin]] slack=[$pe slack]"
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}
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puts "--- find_timing_paths min latch ---"
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set paths_min [find_timing_paths -path_delay min -endpoint_count 10 -group_path_count 20]
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puts "Found [llength $paths_min] min paths"
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foreach pe $paths_min {
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puts " is_latch_check: [$pe is_latch_check] is_check: [$pe is_check] pin=[get_full_name [$pe pin]] slack=[$pe slack]"
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}
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puts "--- Latch path reports with fields ---"
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report_checks -path_delay max -fields {capacitance slew fanout input_pin net}
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report_checks -path_delay min -fields {capacitance slew fanout input_pin net}
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puts "--- set_max_time_borrow ---"
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set_max_time_borrow 2.0 [get_pins latch1/G]
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report_checks -path_delay max -format full_clock_expanded
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set_max_time_borrow 3.0 [get_cells latch1]
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report_checks -path_delay max -format full_clock_expanded
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set_max_time_borrow 4.0 [get_clocks clk]
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report_checks -path_delay max -format full_clock_expanded
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puts "--- report_clock_properties ---"
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report_clock_properties
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puts "--- report_clock_skew ---"
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report_clock_skew -setup
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report_clock_skew -hold
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puts "--- all_registers -level_sensitive ---"
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set ls_cells [all_registers -cells -level_sensitive]
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puts "Level-sensitive cells: [llength $ls_cells]"
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foreach c $ls_cells { puts " [get_full_name $c]" }
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set ls_dpins [all_registers -data_pins -level_sensitive]
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puts "Level-sensitive data pins: [llength $ls_dpins]"
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foreach p $ls_dpins { puts " [get_full_name $p]" }
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set ls_ckpins [all_registers -clock_pins -level_sensitive]
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puts "Level-sensitive clock pins: [llength $ls_ckpins]"
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foreach p $ls_ckpins { puts " [get_full_name $p]" }
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set ls_opins [all_registers -output_pins -level_sensitive]
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puts "Level-sensitive output pins: [llength $ls_opins]"
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foreach p $ls_opins { puts " [get_full_name $p]" }
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puts "--- all_registers -edge_triggered ---"
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set et_cells [all_registers -cells -edge_triggered]
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puts "Edge-triggered cells: [llength $et_cells]"
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foreach c $et_cells { puts " [get_full_name $c]" }
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puts "--- pulse width checks ---"
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report_check_types -min_pulse_width
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report_check_types -min_pulse_width -verbose
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puts "--- min period ---"
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report_clock_min_period
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report_clock_min_period -include_port_paths
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