28 lines
811 B
Verilog
28 lines
811 B
Verilog
module search_crpr_data_checks (clk1, clk2, in1, in2, out1, out2);
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input clk1, clk2, in1, in2;
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output out1, out2;
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wire n1, n2, n3, n4, n5, n6, clk1_buf1, clk1_buf2, clk2_buf;
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// Clock tree 1 with reconvergence
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CLKBUF_X1 ck1buf1 (.A(clk1), .Z(clk1_buf1));
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CLKBUF_X1 ck1buf2 (.A(clk1_buf1), .Z(clk1_buf2));
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// Clock tree 2
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CLKBUF_X1 ck2buf (.A(clk2), .Z(clk2_buf));
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// Combinational logic
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AND2_X1 and1 (.A1(in1), .A2(in2), .ZN(n1));
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BUF_X1 buf1 (.A(n1), .Z(n2));
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// Same-domain register pair (for CRPR)
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DFF_X1 reg1 (.D(n2), .CK(clk1_buf1), .Q(n3));
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BUF_X1 buf2 (.A(n3), .Z(n4));
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DFF_X1 reg2 (.D(n4), .CK(clk1_buf2), .Q(n5));
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// Cross-domain register
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DFF_X1 reg3 (.D(n5), .CK(clk2_buf), .Q(n6));
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BUF_X1 buf3 (.A(n5), .Z(out1));
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BUF_X1 buf4 (.A(n6), .Z(out2));
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endmodule
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