408 lines
13 KiB
Plaintext
408 lines
13 KiB
Plaintext
--- CRPR with propagated clock, setup ---
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Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
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Endpoint: out1 (output port clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock source latency
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0.00 0.00 ^ clk (in)
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0.03 0.03 ^ ckbuf1/Z (CLKBUF_X1)
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0.03 0.05 ^ ckbuf2/Z (CLKBUF_X1)
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0.00 0.05 ^ reg2/CK (DFF_X1)
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0.09 0.14 ^ reg2/Q (DFF_X1)
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0.00 0.14 ^ out1 (out)
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0.14 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (propagated)
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-0.50 9.50 clock uncertainty
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0.00 9.50 clock reconvergence pessimism
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-2.00 7.50 output external delay
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7.50 data required time
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---------------------------------------------------------
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7.50 data required time
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-0.14 data arrival time
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---------------------------------------------------------
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7.36 slack (MET)
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--- CRPR with propagated clock, hold ---
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Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
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Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: min
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock source latency
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0.00 0.00 ^ clk (in)
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0.02 0.02 ^ ckbuf1/Z (CLKBUF_X1)
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0.00 0.02 ^ reg1/CK (DFF_X1)
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0.08 0.11 ^ reg1/Q (DFF_X1)
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0.02 0.13 ^ buf2/Z (BUF_X1)
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0.00 0.13 ^ reg2/D (DFF_X1)
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0.13 data arrival time
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock source latency
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0.00 0.00 ^ clk (in)
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0.03 0.03 ^ ckbuf1/Z (CLKBUF_X1)
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0.03 0.05 ^ ckbuf2/Z (CLKBUF_X1)
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0.00 0.05 ^ reg2/CK (DFF_X1)
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0.30 0.35 clock uncertainty
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0.00 0.35 clock reconvergence pessimism
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0.01 0.36 library hold time
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0.36 data required time
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---------------------------------------------------------
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0.36 data required time
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-0.13 data arrival time
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---------------------------------------------------------
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-0.23 slack (VIOLATED)
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--- report_checks full_clock ---
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Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
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Endpoint: out1 (output port clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock source latency
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0.00 0.00 ^ clk (in)
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0.03 0.03 ^ ckbuf1/Z (CLKBUF_X1)
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0.03 0.05 ^ ckbuf2/Z (CLKBUF_X1)
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0.00 0.05 ^ reg2/CK (DFF_X1)
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0.09 0.14 ^ reg2/Q (DFF_X1)
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0.00 0.14 ^ out1 (out)
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0.14 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (propagated)
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-0.50 9.50 clock uncertainty
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0.00 9.50 clock reconvergence pessimism
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-2.00 7.50 output external delay
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7.50 data required time
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---------------------------------------------------------
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7.50 data required time
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-0.14 data arrival time
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---------------------------------------------------------
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7.36 slack (MET)
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--- report_checks between reg1 and reg2 ---
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Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
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Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock source latency
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0.00 0.00 ^ clk (in)
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0.03 0.03 ^ ckbuf1/Z (CLKBUF_X1)
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0.00 0.03 ^ reg1/CK (DFF_X1)
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0.08 0.11 v reg1/Q (DFF_X1)
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0.02 0.14 v buf2/Z (BUF_X1)
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0.00 0.14 v reg2/D (DFF_X1)
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0.14 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock source latency
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0.00 10.00 ^ clk (in)
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0.02 10.02 ^ ckbuf1/Z (CLKBUF_X1)
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0.02 10.05 ^ ckbuf2/Z (CLKBUF_X1)
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0.00 10.05 ^ reg2/CK (DFF_X1)
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-0.50 9.55 clock uncertainty
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0.00 9.55 clock reconvergence pessimism
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-0.04 9.51 library setup time
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9.51 data required time
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---------------------------------------------------------
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9.51 data required time
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-0.14 data arrival time
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---------------------------------------------------------
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9.38 slack (MET)
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--- report_checks min between reg1 and reg2 ---
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Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
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Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: min
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock source latency
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0.00 0.00 ^ clk (in)
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0.02 0.02 ^ ckbuf1/Z (CLKBUF_X1)
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0.00 0.02 ^ reg1/CK (DFF_X1)
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0.08 0.11 ^ reg1/Q (DFF_X1)
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0.02 0.13 ^ buf2/Z (BUF_X1)
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0.00 0.13 ^ reg2/D (DFF_X1)
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0.13 data arrival time
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock source latency
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0.00 0.00 ^ clk (in)
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0.03 0.03 ^ ckbuf1/Z (CLKBUF_X1)
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0.03 0.05 ^ ckbuf2/Z (CLKBUF_X1)
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0.00 0.05 ^ reg2/CK (DFF_X1)
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0.30 0.35 clock uncertainty
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0.00 0.35 clock reconvergence pessimism
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0.01 0.36 library hold time
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0.36 data required time
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---------------------------------------------------------
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0.36 data required time
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-0.13 data arrival time
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---------------------------------------------------------
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-0.23 slack (VIOLATED)
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--- report_clock_skew ---
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Clock clk
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0.03 source latency reg1/CK ^
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-0.05 target latency reg2/CK ^
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0.50 clock uncertainty
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-0.00 CRPR
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--------------
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0.48 setup skew
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Clock clk
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0.02 source latency reg1/CK ^
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-0.05 target latency reg2/CK ^
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-0.30 clock uncertainty
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-0.00 CRPR
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--------------
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-0.33 hold skew
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--- report_clock_latency ---
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Clock clk
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rise -> rise
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min max
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0.00 0.00 source latency
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0.02 network latency reg1/CK
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0.05 network latency reg2/CK
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---------------
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0.02 0.05 latency
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0.03 skew
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fall -> fall
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min max
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0.00 0.00 source latency
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0.02 network latency reg1/CK
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0.05 network latency reg2/CK
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---------------
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0.02 0.05 latency
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0.03 skew
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--- check CRPR mode settings ---
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CRPR enabled: 1
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CRPR mode: same_pin
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CRPR mode after set: same_pin
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Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
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Endpoint: out1 (output port clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock source latency
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0.00 0.00 ^ clk (in)
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0.03 0.03 ^ ckbuf1/Z (CLKBUF_X1)
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0.03 0.05 ^ ckbuf2/Z (CLKBUF_X1)
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0.00 0.05 ^ reg2/CK (DFF_X1)
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0.09 0.14 ^ reg2/Q (DFF_X1)
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0.00 0.14 ^ out1 (out)
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0.14 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (propagated)
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-0.50 9.50 clock uncertainty
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0.00 9.50 clock reconvergence pessimism
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-2.00 7.50 output external delay
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7.50 data required time
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---------------------------------------------------------
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7.50 data required time
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-0.14 data arrival time
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---------------------------------------------------------
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7.36 slack (MET)
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CRPR mode after set: same_transition
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Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
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Endpoint: out1 (output port clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock source latency
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0.00 0.00 ^ clk (in)
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0.03 0.03 ^ ckbuf1/Z (CLKBUF_X1)
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0.03 0.05 ^ ckbuf2/Z (CLKBUF_X1)
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0.00 0.05 ^ reg2/CK (DFF_X1)
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0.09 0.14 ^ reg2/Q (DFF_X1)
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0.00 0.14 ^ out1 (out)
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0.14 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (propagated)
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-0.50 9.50 clock uncertainty
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0.00 9.50 clock reconvergence pessimism
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-2.00 7.50 output external delay
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7.50 data required time
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---------------------------------------------------------
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7.50 data required time
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-0.14 data arrival time
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---------------------------------------------------------
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7.36 slack (MET)
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--- CRPR disabled ---
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Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
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Endpoint: out1 (output port clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock source latency
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0.00 0.00 ^ clk (in)
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0.03 0.03 ^ ckbuf1/Z (CLKBUF_X1)
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0.03 0.05 ^ ckbuf2/Z (CLKBUF_X1)
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0.00 0.05 ^ reg2/CK (DFF_X1)
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0.09 0.14 ^ reg2/Q (DFF_X1)
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0.00 0.14 ^ out1 (out)
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0.14 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (propagated)
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-0.50 9.50 clock uncertainty
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-2.00 7.50 output external delay
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7.50 data required time
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---------------------------------------------------------
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7.50 data required time
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-0.14 data arrival time
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---------------------------------------------------------
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7.36 slack (MET)
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--- find_timing_paths with CRPR ---
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Warning 502: search_crpr.tcl line 1, find_timing_paths -endpoint_count is deprecated. Use -endpoint_path_count instead.
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Found 3 paths with CRPR
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slack=7.3573676040439295e-9
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slack=7.363725185172143e-9
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slack=8.43751646328883e-9
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--- find_timing_paths min with CRPR ---
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Warning 502: search_crpr.tcl line 1, find_timing_paths -endpoint_count is deprecated. Use -endpoint_path_count instead.
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Found 3 hold paths with CRPR
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slack=-2.327258247225572e-10
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slack=-2.3130949933225509e-10
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slack=7.07958414114529e-10
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--- report_check_types ---
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Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
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Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: min
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.02 0.02 clock network delay (propagated)
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0.00 0.02 ^ reg1/CK (DFF_X1)
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0.08 0.11 ^ reg1/Q (DFF_X1)
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0.02 0.13 ^ buf2/Z (BUF_X1)
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0.00 0.13 ^ reg2/D (DFF_X1)
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0.13 data arrival time
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0.00 0.00 clock clk (rise edge)
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0.05 0.05 clock network delay (propagated)
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0.30 0.35 clock uncertainty
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0.00 0.35 clock reconvergence pessimism
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0.35 ^ reg2/CK (DFF_X1)
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0.01 0.36 library hold time
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0.36 data required time
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---------------------------------------------------------
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0.36 data required time
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-0.13 data arrival time
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---------------------------------------------------------
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-0.23 slack (VIOLATED)
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Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk)
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Endpoint: out1 (output port clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.05 0.05 clock network delay (propagated)
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0.00 0.05 ^ reg2/CK (DFF_X1)
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0.09 0.14 ^ reg2/Q (DFF_X1)
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0.00 0.14 ^ out1 (out)
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0.14 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (propagated)
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-0.50 9.50 clock uncertainty
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0.00 9.50 clock reconvergence pessimism
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-2.00 7.50 output external delay
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7.50 data required time
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---------------------------------------------------------
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7.50 data required time
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-0.14 data arrival time
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---------------------------------------------------------
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7.36 slack (MET)
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max slew
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Pin reg1/QN v
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max slew 0.20
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slew 0.01
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----------------
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Slack 0.19 (MET)
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max capacitance
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Pin ckbuf1/Z ^
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max capacitance 60.73
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capacitance 1.73
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-----------------------
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Slack 59.00 (MET)
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Pin: reg2/CK
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Check: sequential_clock_pulse_width
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.05 0.05 clock network delay (propagated)
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0.00 0.05 reg2/CK
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0.05 open edge arrival time
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5.00 5.00 clock clk (fall edge)
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0.05 5.05 clock network delay (propagated)
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0.00 5.05 reg2/CK
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0.00 5.05 clock reconvergence pessimism
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5.05 close edge arrival time
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---------------------------------------------------------
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0.05 required pulse width (high)
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4.99 actual pulse width
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---------------------------------------------------------
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4.94 slack (MET)
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