80 lines
1.5 KiB
CMake
80 lines
1.5 KiB
CMake
sta_module_tests("search"
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TESTS
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analysis
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annotated_write_verilog
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assigned_delays
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check_timing
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check_types_deep
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clk_skew_interclk
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clk_skew_multiclock
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corner_skew
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crpr
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crpr_data_checks
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data_check_gated
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exception_paths
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fanin_fanout
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fanin_fanout_deep
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gated_clk
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genclk
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genclk_latch_deep
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genclk_property_report
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json_unconstrained
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latch
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latch_timing
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levelize_loop_disabled
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levelize_sim
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limit_violations
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limits_verbose
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min_period_max_skew
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min_period_short
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multiclock
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multicorner_analysis
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network_edit_deep
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network_edit_replace
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network_sta_deep
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path_delay_output
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path_end_types
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path_enum_deep
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path_enum_groups
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path_enum_nworst
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port_pin_properties
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power_activity
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property
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property_deep
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property_extra
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property_inst_cell
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property_libport_deep
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pvt_analysis
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register
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register_deep
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register_filter_combos
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register_latch_sim
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report_fields_formats
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report_formats
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report_gated_datacheck
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report_json_formats
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report_path_detail
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report_path_expanded
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report_path_latch_expanded
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report_path_pvt_cap
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report_path_types
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sdc_advanced
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search_arrival_required
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sim_const_prop
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sim_logic_clk_network
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spef_parasitics
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sta_bidirect_extcap
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sta_cmds
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sta_extra
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tag_path_analysis
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timing
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timing_model
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timing_model_clktree
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timing_model_deep
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timing_model_readback
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worst_slack_sta
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write_sdf_model
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)
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add_subdirectory(cpp)
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