159 lines
7.7 KiB
Plaintext
159 lines
7.7 KiB
Plaintext
###############################################################################
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# Created by write_sdc
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###############################################################################
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current_design sdc_test2
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###############################################################################
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# Timing Constraints
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###############################################################################
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create_clock -name clk1 -period 10.0000 [get_ports {clk1}]
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set_clock_transition -rise -max 0.1500 [get_clocks {clk1}]
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set_clock_transition -fall -min 0.0800 [get_clocks {clk1}]
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set_clock_uncertainty -setup 0.2000 clk1
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set_clock_uncertainty -hold 0.1000 clk1
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set_propagated_clock [get_clocks {clk1}]
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create_clock -name clk2 -period 20.0000 [get_ports {clk2}]
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set_clock_transition 0.1000 [get_clocks {clk2}]
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create_clock -name vclk -period 8.0000
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create_generated_clock -name gclk_div -source [get_ports {clk1}] -divide_by 2 [get_pins {reg1/Q}]
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set_clock_latency 0.2000 [get_clocks {clk2}]
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set_clock_uncertainty -rise_from [get_clocks {clk1}] -rise_to [get_clocks {clk2}] -hold 0.1500
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set_clock_uncertainty -rise_from [get_clocks {clk1}] -rise_to [get_clocks {clk2}] -setup 0.3000
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set_clock_uncertainty -rise_from [get_clocks {clk1}] -fall_to [get_clocks {clk2}] -hold 0.1500
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set_clock_uncertainty -rise_from [get_clocks {clk1}] -fall_to [get_clocks {clk2}] -setup 0.3000
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set_clock_uncertainty -fall_from [get_clocks {clk1}] -rise_to [get_clocks {clk2}] -hold 0.1500
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set_clock_uncertainty -fall_from [get_clocks {clk1}] -rise_to [get_clocks {clk2}] -setup 0.3000
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set_clock_uncertainty -fall_from [get_clocks {clk1}] -fall_to [get_clocks {clk2}] -hold 0.1500
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set_clock_uncertainty -fall_from [get_clocks {clk1}] -fall_to [get_clocks {clk2}] -setup 0.3000
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set_clock_uncertainty -rise_from [get_clocks {clk2}] -rise_to [get_clocks {clk1}] -hold 0.1200
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set_clock_uncertainty -rise_from [get_clocks {clk2}] -rise_to [get_clocks {clk1}] -setup 0.2800
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set_clock_uncertainty -rise_from [get_clocks {clk2}] -fall_to [get_clocks {clk1}] -hold 0.1200
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set_clock_uncertainty -rise_from [get_clocks {clk2}] -fall_to [get_clocks {clk1}] -setup 0.2800
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set_clock_uncertainty -fall_from [get_clocks {clk2}] -rise_to [get_clocks {clk1}] -hold 0.1200
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set_clock_uncertainty -fall_from [get_clocks {clk2}] -rise_to [get_clocks {clk1}] -setup 0.2800
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set_clock_uncertainty -fall_from [get_clocks {clk2}] -fall_to [get_clocks {clk1}] -hold 0.1200
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set_clock_uncertainty -fall_from [get_clocks {clk2}] -fall_to [get_clocks {clk1}] -setup 0.2800
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set_sense -type clock -positive -clock [get_clocks {clk1}] [get_pins {buf1/Z}]
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set_clock_groups -name async1 -asynchronous \
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-group [get_clocks {clk2}]\
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-group [list [get_clocks {clk1}]\
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[get_clocks {gclk_div}]]
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set_input_delay 2.0000 -clock [get_clocks {clk1}] -add_delay [get_ports {in1}]
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set_input_delay 2.5000 -clock [get_clocks {clk1}] -rise -max -add_delay [get_ports {in2}]
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set_input_delay 1.0000 -clock [get_clocks {clk1}] -fall -min -add_delay [get_ports {in2}]
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set_input_delay 1.5000 -clock [get_clocks {clk1}] -clock_fall -add_delay [get_ports {in3}]
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set_input_delay 1.8000 -clock [get_clocks {clk2}] -add_delay [get_ports {in3}]
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set_output_delay 3.0000 -clock [get_clocks {clk1}] -add_delay [get_ports {out1}]
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set_output_delay 3.5000 -clock [get_clocks {clk2}] -rise -max -add_delay [get_ports {out2}]
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set_output_delay 1.5000 -clock [get_clocks {clk2}] -fall -min -add_delay [get_ports {out2}]
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set_disable_timing -from {A1} -to {ZN} [get_lib_cells {NangateOpenCellLibrary/AND2_X1}]
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set_disable_timing [get_lib_cells {NangateOpenCellLibrary/NOR2_X1}]
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set_disable_timing [get_cells {buf1}]
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group_path -name grp_clk1\
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-from [get_clocks {clk1}]
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group_path -name grp_io\
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-from [get_ports {in1}]\
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-to [get_ports {out1}]
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group_path -name grp_thru\
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-from [get_ports {in2}]\
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-through [get_nets {n2}]\
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-to [get_ports {out1}]
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group_path -default\
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-from [get_ports {in3}]\
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-to [get_ports {out2}]
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set_multicycle_path -hold\
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-from [get_ports {in1}]\
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-to [get_ports {out1}] 1
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set_multicycle_path -hold -end\
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-from [get_ports {in2}]\
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-to [get_ports {out2}] 1
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set_multicycle_path -setup\
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-from [get_ports {in1}]\
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-to [get_ports {out1}] 2
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set_multicycle_path -setup -start\
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-from [get_ports {in2}]\
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-to [get_ports {out2}] 3
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set_min_delay\
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-from [get_ports {in2}]\
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-to [get_ports {out1}] 1.0000
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set_max_delay\
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-from [get_ports {in2}]\
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-to [get_ports {out1}] 8.0000
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set_max_delay\
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-from [get_ports {in3}]\
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-through [get_cells {or1}]\
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-to [get_ports {out2}] 7.0000
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set_false_path -hold\
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-from [get_clocks {vclk}]\
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-to [get_clocks {clk1}]
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set_false_path -setup\
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-from [get_clocks {clk1}]\
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-to [get_clocks {vclk}]
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set_false_path\
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-from [get_clocks {clk1}]\
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-to [get_clocks {clk2}]
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set_false_path\
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-from [get_ports {in1}]\
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-through [get_pins {and1/ZN}]\
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-to [get_ports {out1}]
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set_false_path\
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-from [get_ports {in2}]\
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-rise_through [get_pins {buf1/Z}]\
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-fall_through [get_nets {n3}]\
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-to [get_ports {out1}]
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set_false_path\
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-rise_from [get_ports {in3}]\
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-fall_to [get_ports {out2}]
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set_data_check -from [get_pins {reg1/Q}] -to [get_pins {reg2/D}] -hold 0.3000
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set_data_check -from [get_pins {reg1/Q}] -to [get_pins {reg2/D}] -setup 0.5000
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###############################################################################
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# Environment
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###############################################################################
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set_operating_conditions typical
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set_wire_load_mode "enclosed"
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set_load -pin_load -min 0.0100 [get_ports {out1}]
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set_load -pin_load -max 0.0600 [get_ports {out1}]
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set_load -wire_load 0.0200 [get_ports {out1}]
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set_port_fanout_number 4 [get_ports {out1}]
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set_load -pin_load -rise 0.0400 [get_ports {out2}]
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set_load -pin_load -fall 0.0450 [get_ports {out2}]
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set_load 0.0100 [get_nets {n1}]
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set_load 0.0200 [get_nets {n2}]
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set_drive -rise 100.0000 [get_ports {in1}]
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set_drive -fall 100.0000 [get_ports {in1}]
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set_drive -rise 80.0000 [get_ports {in2}]
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set_drive -fall 120.0000 [get_ports {in2}]
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set_driving_cell -lib_cell BUF_X1 -pin {Z} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {in1}]
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set_driving_cell -lib_cell INV_X1 -pin {ZN} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {in2}]
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set_driving_cell -lib_cell BUF_X4 -pin {Z} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {in3}]
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set_input_transition 0.1500 [get_ports {in1}]
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set_input_transition -rise -max 0.1200 [get_ports {in2}]
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set_input_transition -fall -min 0.0800 [get_ports {in2}]
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set_resistance 10.0000 -min [get_nets {n1}]
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set_resistance 20.0000 -max [get_nets {n1}]
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set_logic_one [get_ports {in2}]
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set_case_analysis 0 [get_ports {in3}]
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set_timing_derate -cell_delay -early -clock 0.9700
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set_timing_derate -cell_delay -early -data 0.9500
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set_timing_derate -net_delay -early -clock 0.9700
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set_timing_derate -net_delay -early -data 0.9500
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set_timing_derate -cell_delay -late -clock 1.0300
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set_timing_derate -cell_delay -late -data 1.0500
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set_timing_derate -net_delay -late -clock 1.0300
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set_timing_derate -net_delay -late -data 1.0500
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###############################################################################
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# Design Rules
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###############################################################################
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set_min_pulse_width -high 0.6000 [get_clocks {clk1}]
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set_min_pulse_width -low 0.4000 [get_clocks {clk1}]
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set_min_pulse_width 0.5500 [get_clocks {clk2}]
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set_max_time_borrow 1.5000 [get_pins {reg1/D}]
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set_max_time_borrow 2.0000 [get_clocks {clk1}]
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set_max_transition 0.5000 [current_design]
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set_max_transition 0.3000 [get_ports {out1}]
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set_max_transition -clock_path 0.2000 [get_clocks {clk1}]
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set_max_transition -data_path 0.4000 [get_clocks {clk1}]
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set_max_capacitance 0.2000 [current_design]
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set_max_capacitance 0.1000 [get_ports {out1}]
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set_max_fanout 20.0000 [current_design]
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set_max_area 100.0000
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