155 lines
5.5 KiB
Tcl
155 lines
5.5 KiB
Tcl
# Test advanced generated clock options and clock model queries for code coverage
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# Targets: Clock.cc (generated clock model, edge-based, master clock),
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# WriteSdc.cc (writeGeneratedClock, writeClockPins),
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# Sdc.cc (clock creation and deletion paths)
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source ../../test/helpers.tcl
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read_liberty ../../test/nangate45/Nangate45_typ.lib
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read_verilog sdc_test2.v
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link_design sdc_test2
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############################################################
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# Multiple clocks on same port and various generated clocks
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############################################################
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# Base clocks
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create_clock -name clk1 -period 10 [get_ports clk1]
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create_clock -name clk2 -period 20 -waveform {0 10} [get_ports clk2]
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# Virtual clock (no pin)
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create_clock -name vclk -period 8
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# Multiple clocks on same port (-add)
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create_clock -name clk1_2x -period 5 -add [get_ports clk1]
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# Asymmetric waveform clock
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create_clock -name clk_asym -period 12 -waveform {0 3} -add [get_ports clk2]
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# Report clock properties
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report_clock_properties
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############################################################
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# Generated clocks - divide_by
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############################################################
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create_generated_clock -name gclk_div2 -source [get_ports clk1] -divide_by 2 [get_pins reg1/Q]
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create_generated_clock -name gclk_div3 -source [get_ports clk2] -divide_by 3 [get_pins reg3/Q]
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############################################################
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# Generated clocks - multiply_by
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############################################################
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create_generated_clock -name gclk_mul2 -source [get_ports clk1] -multiply_by 2 [get_pins reg2/Q]
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############################################################
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# Generated clocks - edges
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############################################################
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############################################################
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# Report clock properties after generated clocks
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############################################################
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report_clock_properties
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############################################################
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# Clock constraints on generated clocks
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############################################################
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# Source latency on generated clock
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set_clock_latency -source 0.3 [get_clocks gclk_div2]
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set_clock_latency -source -rise -max 0.4 [get_clocks gclk_div2]
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set_clock_latency -source -fall -min 0.1 [get_clocks gclk_div2]
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# Network latency on generated clock
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set_clock_latency 0.15 [get_clocks gclk_div3]
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# Clock uncertainty on generated clocks
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set_clock_uncertainty -setup 0.15 [get_clocks gclk_div2]
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set_clock_uncertainty -hold 0.08 [get_clocks gclk_div2]
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# Inter-clock uncertainty between generated and base
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set_clock_uncertainty -from [get_clocks clk1] -to [get_clocks gclk_div2] -setup 0.2
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set_clock_uncertainty -from [get_clocks gclk_div2] -to [get_clocks clk2] -hold 0.1
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# Clock transition on generated clock
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set_clock_transition 0.12 [get_clocks gclk_div2]
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set_clock_transition -rise -max 0.15 [get_clocks gclk_mul2]
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# Propagated clock on generated
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set_propagated_clock [get_clocks gclk_div2]
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############################################################
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# IO delays referencing generated clocks
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############################################################
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set_input_delay -clock gclk_div2 3.0 [get_ports in1]
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set_input_delay -clock gclk_div2 -rise -max 3.5 [get_ports in2]
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set_input_delay -clock gclk_div2 -fall -min 1.5 [get_ports in2]
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set_output_delay -clock gclk_mul2 2.0 [get_ports out1]
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set_output_delay -clock gclk_div3 2.5 [get_ports out2]
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############################################################
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# Clock groups involving generated clocks
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############################################################
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set_clock_groups -asynchronous -name genclk_async \
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-group {clk1 clk1_2x gclk_div2 gclk_mul2} -group {clk2 gclk_div3}
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############################################################
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# Exception paths referencing generated clocks
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############################################################
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set_false_path -from [get_clocks gclk_div2] -to [get_clocks gclk_div3]
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set_multicycle_path -setup 3 -from [get_clocks clk1] -to [get_clocks gclk_div2]
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############################################################
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# Write SDC (exercises generated clock writing)
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############################################################
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set sdc_file1 [make_result_file sdc_genclk_native.sdc]
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write_sdc -no_timestamp $sdc_file1
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diff_files sdc_genclk_native.sdcok $sdc_file1
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set sdc_file2 [make_result_file sdc_genclk_compat.sdc]
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write_sdc -no_timestamp -compatible $sdc_file2
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diff_files sdc_genclk_compat.sdcok $sdc_file2
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set sdc_file3 [make_result_file sdc_genclk_d6.sdc]
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write_sdc -no_timestamp -digits 6 $sdc_file3
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diff_files sdc_genclk_d6.sdcok $sdc_file3
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############################################################
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# Report checks
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############################################################
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report_checks -from [get_ports in1] -to [get_ports out1]
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report_checks -from [get_ports in2] -to [get_ports out2]
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############################################################
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# Delete and re-create clocks (exercises Clock.cc deletion)
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############################################################
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# Remove clock groups first
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unset_clock_groups -asynchronous -name genclk_async
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# Delete generated clocks
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delete_generated_clock [get_clocks gclk_mul2]
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# Unset latencies on gclk_div2 before delete
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unset_clock_latency [get_clocks gclk_div2]
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unset_clock_latency -source [get_clocks gclk_div2]
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unset_propagated_clock [get_clocks gclk_div2]
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delete_generated_clock [get_clocks gclk_div2]
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delete_generated_clock [get_clocks gclk_div3]
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# Delete virtual clock
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delete_clock [get_clocks vclk]
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report_clock_properties
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