216 lines
7.7 KiB
Plaintext
216 lines
7.7 KiB
Plaintext
Warning 1061: generated clock gclk_div2 pin clk1 is in the fanout of multiple clocks.
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Warning 1061: generated clock gclk_div4 pin clk1 is in the fanout of multiple clocks.
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Startpoint: reg3/Q (clock source 'gclk_mul2')
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Endpoint: out2 (output port clocked by clk_aux)
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Path Group: clk_aux
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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15.00 15.00 clock gclk_mul2 (fall edge)
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0.00 15.00 clock network delay
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15.00 v out2 (out)
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15.00 data arrival time
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20.00 20.00 clock clk_aux (rise edge)
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0.20 20.20 clock network delay (ideal)
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0.00 20.20 clock reconvergence pessimism
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-2.80 17.40 output external delay
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17.40 data required time
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---------------------------------------------------------
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17.40 data required time
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-15.00 data arrival time
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---------------------------------------------------------
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2.40 slack (MET)
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Startpoint: in1 (input port clocked by clk_master)
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Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk_master)
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Path Group: clk_master
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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5.00 5.00 clock clk_master (fall edge)
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0.60 5.60 clock network delay (propagated)
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2.50 8.10 v input external delay
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0.00 8.10 v in1 (in)
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0.02 8.12 v buf1/Z (BUF_X1)
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0.05 8.17 v or1/ZN (OR2_X1)
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0.03 8.19 ^ nor1/ZN (NOR2_X1)
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0.00 8.19 ^ reg2/D (DFF_X1)
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8.19 data arrival time
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10.00 10.00 clock clk_master (rise edge)
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0.30 10.30 clock network delay (propagated)
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-0.15 10.15 clock uncertainty
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0.00 10.15 clock reconvergence pessimism
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10.15 ^ reg2/CK (DFF_X1)
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-0.03 10.12 library setup time
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10.12 data required time
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---------------------------------------------------------
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10.12 data required time
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-8.19 data arrival time
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---------------------------------------------------------
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1.92 slack (MET)
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Startpoint: in1 (input port clocked by clk_master)
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Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk_master_alt)
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Path Group: clk_master_alt
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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5.00 5.00 clock clk_master (fall edge)
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0.60 5.60 clock network delay (propagated)
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2.50 8.10 v input external delay
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0.00 8.10 v in1 (in)
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0.02 8.12 v buf1/Z (BUF_X1)
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0.05 8.17 v or1/ZN (OR2_X1)
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0.03 8.19 ^ nor1/ZN (NOR2_X1)
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0.00 8.19 ^ reg2/D (DFF_X1)
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8.19 data arrival time
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10.00 10.00 clock clk_master_alt (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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10.00 ^ reg2/CK (DFF_X1)
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-0.03 9.97 library setup time
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9.97 data required time
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---------------------------------------------------------
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9.97 data required time
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-8.19 data arrival time
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---------------------------------------------------------
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1.77 slack (MET)
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Startpoint: reg2/Q (clock source 'gclk_div4')
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Endpoint: out1 (output port clocked by gclk_div2)
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Path Group: gclk_div2
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock gclk_div4 (rise edge)
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0.00 0.00 clock network delay
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0.00 ^ out1 (out)
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0.00 data arrival time
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10.00 10.00 clock gclk_div2 (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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-3.50 6.50 output external delay
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6.50 data required time
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---------------------------------------------------------
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6.50 data required time
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-0.00 data arrival time
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---------------------------------------------------------
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6.50 slack (MET)
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Clock Period Waveform
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----------------------------------------------------
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clk_master 10.00 0.00 5.00
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clk_aux 20.00 0.00 10.00
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gclk_div2 10.00 0.00 5.00 (generated)
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gclk_div4 20.00 0.00 10.00 (generated)
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gclk_mul2 10.00 0.00 5.00 (generated)
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clk_master_alt 5.00 0.00 2.50
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Clock Period Waveform
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----------------------------------------------------
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clk_master 10.00 0.00 5.00
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clk_aux 20.00 0.00 10.00
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clk_master_alt 5.00 0.00 2.50
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Clock Period Waveform
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----------------------------------------------------
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clk_master 10.00 0.00 5.00
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Startpoint: in1 (input port clocked by clk_master)
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Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk_master)
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Path Group: clk_master
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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5.00 5.00 clock clk_master (fall edge)
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0.60 5.60 clock network delay (propagated)
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2.50 8.10 v input external delay
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0.00 8.10 v in1 (in)
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0.02 8.12 v buf1/Z (BUF_X1)
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0.05 8.17 v or1/ZN (OR2_X1)
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0.03 8.19 ^ nor1/ZN (NOR2_X1)
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0.00 8.19 ^ reg2/D (DFF_X1)
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8.19 data arrival time
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10.00 10.00 clock clk_master (rise edge)
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0.30 10.30 clock network delay (propagated)
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-0.15 10.15 clock uncertainty
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0.00 10.15 clock reconvergence pessimism
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10.15 ^ reg2/CK (DFF_X1)
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-0.03 10.12 library setup time
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10.12 data required time
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---------------------------------------------------------
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10.12 data required time
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-8.19 data arrival time
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---------------------------------------------------------
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1.92 slack (MET)
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Startpoint: in1 (input port clocked by clk_master)
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Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk_master)
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Path Group: clk_master
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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5.00 5.00 clock clk_master (fall edge)
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0.60 5.60 clock network delay (propagated)
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2.50 8.10 v input external delay
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0.00 8.10 v in1 (in)
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0.02 8.12 v buf1/Z (BUF_X1)
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0.05 8.17 v or1/ZN (OR2_X1)
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0.03 8.19 ^ nor1/ZN (NOR2_X1)
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0.00 8.19 ^ reg2/D (DFF_X1)
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8.19 data arrival time
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10.00 10.00 clock clk_master (rise edge)
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0.30 10.30 clock network delay (propagated)
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-0.15 10.15 clock uncertainty
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0.00 10.15 clock reconvergence pessimism
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10.15 ^ reg2/CK (DFF_X1)
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-0.03 10.12 library setup time
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10.12 data required time
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---------------------------------------------------------
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10.12 data required time
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-8.19 data arrival time
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---------------------------------------------------------
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1.92 slack (MET)
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Startpoint: reg3 (rising edge-triggered flip-flop clocked by clk_new)
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Endpoint: out2 (output port clocked by clk_new)
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Path Group: clk_new
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk_new (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 ^ reg3/CK (DFF_X1)
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0.08 0.08 ^ reg3/Q (DFF_X1)
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0.00 0.08 ^ out2 (out)
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0.08 data arrival time
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15.00 15.00 clock clk_new (rise edge)
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0.00 15.00 clock network delay (ideal)
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0.00 15.00 clock reconvergence pessimism
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-3.00 12.00 output external delay
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12.00 data required time
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---------------------------------------------------------
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12.00 data required time
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-0.08 data arrival time
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---------------------------------------------------------
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11.92 slack (MET)
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