265 lines
5.5 KiB
Plaintext
265 lines
5.5 KiB
Plaintext
Startpoint: in1 (input port clocked by clk)
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Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 v input external delay
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0.00 0.00 v in1 (in)
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0.06 0.06 v buf_in/Z (BUF_X1)
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0.03 0.08 v sub1/and_gate/ZN (AND2_X1)
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0.02 0.11 v sub1/buf_gate/Z (BUF_X1)
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0.02 0.13 v sub2/and_gate/ZN (AND2_X1)
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0.03 0.16 v sub2/buf_gate/Z (BUF_X1)
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0.01 0.17 ^ inv1/ZN (INV_X1)
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0.00 0.17 ^ reg1/D (DFF_X1)
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0.17 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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10.00 ^ reg1/CK (DFF_X1)
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-0.03 9.97 library setup time
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9.97 data required time
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---------------------------------------------------------
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9.97 data required time
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-0.17 data arrival time
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---------------------------------------------------------
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9.80 slack (MET)
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--- pin direction queries ---
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in1 is input port
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out1 is output port
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reg1/CK direction: input
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reg1/D direction: input
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reg1/Q direction: output
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pin buf_in/A: dir=input
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pin buf_in/Z: dir=output
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pin inv1/A: dir=input
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pin inv1/ZN: dir=output
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pin buf_out1/A: dir=input
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pin buf_out1/Z: dir=output
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pin buf_out2/A: dir=input
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pin buf_out2/Z: dir=output
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--- hierarchical queries ---
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hierarchical cells: 11
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hierarchical pins: 30
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hierarchical nets: 19
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sub* hierarchical cells: 2
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buf* hierarchical cells: 5
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--- fanin/fanout variants ---
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fanin flat to out1: 5
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fanin cells to out1: 3
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fanin startpoints to out1: 1
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fanout flat from in1: 17
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fanout cells from in1: 2
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fanout endpoints from in1: 0
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fanin levels=1 to out1: 3
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fanin levels=2 to out1: 5
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fanin levels=3 to out1: 5
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fanin pin_levels=1 to out1: 2
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fanin pin_levels=2 to out1: 3
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fanout levels=1 from in1: 3
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fanout levels=2 from in1: 5
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fanout pin_levels=1 from in1: 2
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fanout pin_levels=2 from in1: 3
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fanin trace_arcs timing to out1: 5
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fanin trace_arcs enabled to out1: 5
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fanin trace_arcs all to out1: 5
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fanout trace_arcs all from in1: 17
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fanin flat to out2: 18
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fanin cells to out2: 2
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fanout flat from in2: 15
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fanout flat from in3: 11
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--- report_net all ---
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Net w1
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Pin capacitance: 0.87-0.92
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Wire capacitance: 0.00
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Total capacitance: 0.87-0.92
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Number of drivers: 1
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Number of loads: 1
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Number of pins: 2
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Driver pins
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buf_in/Z output (BUF_X1)
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Load pins
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sub1/and_gate/A1 input (AND2_X1) 0.87-0.92
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Hierarchical pins
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sub1/A input
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report_net w1: done
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Net w2
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Pin capacitance: 0.87-0.92
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Wire capacitance: 0.00
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Total capacitance: 0.87-0.92
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Number of drivers: 1
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Number of loads: 1
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Number of pins: 2
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Driver pins
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sub1/buf_gate/Z output (BUF_X1)
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Load pins
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sub2/and_gate/A1 input (AND2_X1) 0.87-0.92
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Hierarchical pins
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sub1/Y output
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sub2/A input
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report_net w2: done
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Net w3
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Pin capacitance: 2.42-2.67
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Wire capacitance: 0.00
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Total capacitance: 2.42-2.67
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Number of drivers: 1
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Number of loads: 2
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Number of pins: 3
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Driver pins
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sub2/buf_gate/Z output (BUF_X1)
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Load pins
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buf_out2/A input (BUF_X1) 0.88-0.97
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inv1/A input (INV_X1) 1.55-1.70
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Hierarchical pins
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sub2/Y output
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report_net w3: done
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Net w4
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Pin capacitance: 1.06-1.14
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Wire capacitance: 0.00
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Total capacitance: 1.06-1.14
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Number of drivers: 1
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Number of loads: 1
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Number of pins: 2
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Driver pins
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inv1/ZN output (INV_X1)
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Load pins
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reg1/D input (DFF_X1) 1.06-1.14
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report_net w4: done
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Net w5
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Pin capacitance: 1.59-1.78
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Wire capacitance: 0.00
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Total capacitance: 1.59-1.78
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Number of drivers: 1
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Number of loads: 1
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Number of pins: 2
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Driver pins
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reg1/Q output (DFF_X1)
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Load pins
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buf_out1/A input (BUF_X2) 1.59-1.78
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report_net w5: done
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--- report_instance all ---
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Instance buf_in
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Cell: BUF_X1
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Library: NangateOpenCellLibrary
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Path cells: BUF_X1
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Input pins:
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A input in1
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Output pins:
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Z output w1
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Other pins:
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VDD power (unconnected)
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VSS ground (unconnected)
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Instance sub1
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Cell: sub_block
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Library: verilog
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Path cells: sub_block
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Input pins:
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A input w1
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B input in2
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Output pins:
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Y output w2
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Children:
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and_gate (AND2_X1)
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buf_gate (BUF_X1)
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Instance sub2
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Cell: sub_block
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Library: verilog
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Path cells: sub_block
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Input pins:
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A input w2
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B input in3
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Output pins:
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Y output w3
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Children:
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and_gate (AND2_X1)
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buf_gate (BUF_X1)
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Instance inv1
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Cell: INV_X1
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Library: NangateOpenCellLibrary
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Path cells: INV_X1
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Input pins:
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A input w3
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Output pins:
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ZN output w4
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Other pins:
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VDD power (unconnected)
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VSS ground (unconnected)
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Instance reg1
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Cell: DFF_X1
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Library: NangateOpenCellLibrary
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Path cells: DFF_X1
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Input pins:
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D input w4
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CK input clk
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Output pins:
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Q output w5
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QN output (unconnected)
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Other pins:
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VDD power (unconnected)
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VSS ground (unconnected)
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IQ internal (unconnected)
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IQN internal (unconnected)
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Instance buf_out1
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Cell: BUF_X2
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Library: NangateOpenCellLibrary
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Path cells: BUF_X2
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Input pins:
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A input w5
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Output pins:
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Z output out1
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Other pins:
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VDD power (unconnected)
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VSS ground (unconnected)
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Instance buf_out2
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Cell: BUF_X1
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Library: NangateOpenCellLibrary
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Path cells: BUF_X1
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Input pins:
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A input w3
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Output pins:
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Z output out2
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Other pins:
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VDD power (unconnected)
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VSS ground (unconnected)
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--- all_registers ---
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all_registers: 1
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register data_pins: 1
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register clock_pins: 1
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register output_pins: 2
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--- port direction filters ---
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input ports: 4
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output ports: 2
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--- cell ref_name filters ---
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BUF_X1: 2
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DFF_X1: 1
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INV_X1: 1
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--- instance/pin/net count queries ---
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top level cells: 7
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top level nets: 11
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top level pins: 20
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