206 lines
5.0 KiB
Plaintext
206 lines
5.0 KiB
Plaintext
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
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Endpoint: out1 (output port clocked by clk)
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Path Group: clk
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Path Type: max
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Corner: fast
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 ^ reg1/CK (DFF_X1)
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0.05 0.05 v reg1/Q (DFF_X1)
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0.00 0.05 v out1 (out)
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0.05 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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-3.00 7.00 output external delay
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7.00 data required time
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---------------------------------------------------------
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7.00 data required time
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-0.05 data arrival time
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---------------------------------------------------------
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6.95 slack (MET)
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Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
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Endpoint: out1 (output port clocked by clk)
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Path Group: clk
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Path Type: max
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Corner: slow
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 ^ reg1/CK (DFF_X1)
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0.29 0.29 ^ reg1/Q (DFF_X1)
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0.00 0.29 ^ out1 (out)
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0.29 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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-3.00 7.00 output external delay
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7.00 data required time
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---------------------------------------------------------
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7.00 data required time
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-0.29 data arrival time
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---------------------------------------------------------
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6.71 slack (MET)
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Clock Period Waveform
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----------------------------------------------------
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clk 10.00 0.00 5.00
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Startpoint: in1 (input port clocked by clk)
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Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: min
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Corner: fast
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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2.00 2.00 ^ input external delay
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0.00 2.00 ^ in1 (in)
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0.01 2.01 ^ buf1/Z (BUF_X1)
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0.00 2.01 ^ reg1/D (DFF_X1)
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2.01 data arrival time
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 clock reconvergence pessimism
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0.00 ^ reg1/CK (DFF_X1)
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0.00 0.00 library hold time
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0.00 data required time
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---------------------------------------------------------
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0.00 data required time
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-2.01 data arrival time
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---------------------------------------------------------
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2.01 slack (MET)
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Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
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Endpoint: out1 (output port clocked by clk)
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Path Group: clk
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Path Type: max
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Corner: slow
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 ^ reg1/CK (DFF_X1)
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0.29 0.29 ^ reg1/Q (DFF_X1)
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0.00 0.29 ^ out1 (out)
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0.29 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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-3.00 7.00 output external delay
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7.00 data required time
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---------------------------------------------------------
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7.00 data required time
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-0.29 data arrival time
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---------------------------------------------------------
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6.71 slack (MET)
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Cell BUF_X1
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Library NangateOpenCellLibrary_fast
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File ../../test/nangate45/Nangate45_fast.lib
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VDD power
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VSS ground
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A input 0.91-0.98
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Z output function=A
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Timing arcs
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A -> Z
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combinational
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^ -> ^
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v -> v
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Cell BUF_X1
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Library NangateOpenCellLibrary_slow
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File ../../test/nangate45/Nangate45_slow.lib
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VDD power
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VSS ground
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A input 0.84-0.93
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Z output function=A
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Timing arcs
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A -> Z
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combinational
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^ -> ^
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v -> v
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Cell DFF_X1
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Library NangateOpenCellLibrary_fast
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File ../../test/nangate45/Nangate45_fast.lib
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VDD power
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VSS ground
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D input 1.10-1.16
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CK input 0.89-0.97
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Q output function=IQ
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QN output function=IQN
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IQ internal
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IQN internal
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Timing arcs
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CK -> D
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hold
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^ -> ^
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^ -> v
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CK -> D
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setup
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^ -> ^
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^ -> v
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CK -> CK
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width
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^ -> v
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v -> ^
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CK -> Q
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Reg Clk to Q
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^ -> ^
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^ -> v
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CK -> QN
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Reg Clk to Q
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^ -> ^
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^ -> v
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Cell DFF_X1
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Library NangateOpenCellLibrary_slow
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File ../../test/nangate45/Nangate45_slow.lib
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VDD power
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VSS ground
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D input 1.03-1.11
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CK input 0.82-0.91
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Q output function=IQ
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QN output function=IQN
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IQ internal
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IQN internal
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Timing arcs
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CK -> D
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hold
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^ -> ^
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^ -> v
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CK -> D
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setup
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^ -> ^
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^ -> v
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CK -> CK
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width
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^ -> v
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v -> ^
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CK -> Q
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Reg Clk to Q
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^ -> ^
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^ -> v
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CK -> QN
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Reg Clk to Q
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^ -> ^
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^ -> v
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