162 lines
6.1 KiB
Tcl
162 lines
6.1 KiB
Tcl
# Deep cell property queries: timing arc traversal, port capacitance,
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# sequential elements, leakage/internal power, and cell classification.
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source ../../test/helpers.tcl
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############################################################
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# Read libraries
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############################################################
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read_liberty ../../test/nangate45/Nangate45_typ.lib
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read_liberty ../../test/asap7/asap7sc7p5t_SEQ_RVT_FF_nldm_220123.lib
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read_liberty ../../test/ihp-sg13g2/sg13g2_stdcell_typ_1p20V_25C.lib
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############################################################
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# Port capacitance queries
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# Exercises: LibertyPort capacitance getters/setters
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############################################################
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set inv_a [get_lib_pin NangateOpenCellLibrary/INV_X1/A]
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set inv_zn [get_lib_pin NangateOpenCellLibrary/INV_X1/ZN]
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set cap_a [get_property $inv_a capacitance]
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set cap_zn [get_property $inv_zn capacitance]
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# DFF capacitance queries
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set dff_ck [get_lib_pin NangateOpenCellLibrary/DFF_X1/CK]
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set cap_ck [get_property $dff_ck capacitance]
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set dff_d [get_lib_pin NangateOpenCellLibrary/DFF_X1/D]
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set cap_d [get_property $dff_d capacitance]
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# Larger drive strengths have different capacitances
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foreach size {1 2 4 8 16 32} {
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set pin [get_lib_pin NangateOpenCellLibrary/INV_X${size}/A]
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set cap [get_property $pin capacitance]
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puts "INV_X${size}/A cap = $cap"
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}
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foreach size {1 2 4 8 16 32} {
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set pin [get_lib_pin NangateOpenCellLibrary/BUF_X${size}/A]
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set cap [get_property $pin capacitance]
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puts "BUF_X${size}/A cap = $cap"
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}
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############################################################
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# Cell area queries
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############################################################
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foreach cell_name {INV_X1 INV_X2 INV_X4 INV_X8 INV_X16 INV_X32
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BUF_X1 BUF_X2 BUF_X4 BUF_X8 BUF_X16 BUF_X32
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DFF_X1 DFF_X2 DFFR_X1 DFFS_X1 DFFRS_X1
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NAND2_X1 NAND2_X2 NAND2_X4
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NOR2_X1 NOR2_X2 NOR2_X4
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AOI21_X1 OAI21_X1 MUX2_X1 FA_X1 HA_X1
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TINV_X1 CLKGATETST_X1} {
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set cell [get_lib_cell NangateOpenCellLibrary/$cell_name]
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set area [get_property $cell area]
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puts "$cell_name area = $area"
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}
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############################################################
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# Cell dont_use, is_macro, is_memory queries
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############################################################
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foreach cell_name {INV_X1 BUF_X1 DFF_X1 ANTENNA_X1 FILLCELL_X1} {
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set cell [get_lib_cell NangateOpenCellLibrary/$cell_name]
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set du [get_property $cell dont_use]
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puts "$cell_name dont_use = $du"
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}
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############################################################
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# Leakage power queries
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############################################################
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############################################################
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# Timing arc property queries
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# Exercises: arc direction, sense, timing_type
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############################################################
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# Setup a design and run timing to exercise arc evaluation
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read_verilog ../../sdc/test/sdc_test2.v
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link_design sdc_test2
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create_clock -name clk1 -period 10 [get_ports clk1]
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create_clock -name clk2 -period 20 [get_ports clk2]
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set_input_delay -clock clk1 2.0 [get_ports {in1 in2 in3}]
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set_output_delay -clock clk1 3.0 [all_outputs]
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set_input_transition 0.1 [all_inputs]
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# Detailed timing reports exercise arc evaluation
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report_checks -from [get_ports in1] -to [get_ports out1] -path_delay max
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report_checks -from [get_ports in1] -to [get_ports out1] -path_delay min
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report_checks -from [get_ports in2] -to [get_ports out2]
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# Rise/fall reports exercise different arc transitions
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report_checks -rise_from [get_ports in1] -to [get_ports out1]
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report_checks -fall_from [get_ports in1] -to [get_ports out1]
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report_checks -from [get_ports in1] -rise_to [get_ports out1]
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report_checks -from [get_ports in1] -fall_to [get_ports out1]
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############################################################
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# Report check types exercises different check arc types
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############################################################
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report_check_types -max_delay -min_delay
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report_check_types -max_slew -max_capacitance -max_fanout
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report_check_types -recovery -removal
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report_check_types -min_pulse_width -min_period
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report_check_types -clock_gating_setup -clock_gating_hold
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report_check_types -max_skew
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############################################################
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# Report power to exercise internal power model paths
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############################################################
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report_power
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report_power -instances [get_cells *]
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############################################################
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# Sky130 cells - different tristate and latch cells
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############################################################
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read_liberty ../../test/sky130hd/sky130hd_tt.lib
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# Tristate buffer
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report_lib_cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__ebufn_1
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report_lib_cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__ebufn_2
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report_lib_cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__ebufn_4
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# Latch cells
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report_lib_cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxtp_1
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report_lib_cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dlxtn_1
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# Scan flip-flops
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report_lib_cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sdfxtp_1
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report_lib_cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__sdfxbp_1
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# DFF with async set/clear (exercises recovery/removal)
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report_lib_cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dfxtp_1
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report_lib_cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dfrtp_1
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report_lib_cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dfstp_1
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report_lib_cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__dfbbp_1
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# Mux cells
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report_lib_cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__mux2_1
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report_lib_cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__mux2i_1
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report_lib_cell sky130_fd_sc_hd__tt_025C_1v80/sky130_fd_sc_hd__mux4_1
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############################################################
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# Write roundtrip to exercise all writer cell/arc/model paths
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############################################################
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set outfile [make_result_file liberty_cell_deep_write.lib]
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sta::write_liberty NangateOpenCellLibrary $outfile
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# Verify file contents against static golden.
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diff_files liberty_cell_deep_write.libok $outfile
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