90 lines
3.1 KiB
Plaintext
90 lines
3.1 KiB
Plaintext
INV_X1 is_leaf = 1
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INV_X1 is_buffer = 0
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INV_X1 is_inverter = 1
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BUF_X1 is_leaf = 1
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BUF_X1 is_buffer = 1
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BUF_X1 is_inverter = 0
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NAND2_X1 is_leaf = 1
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NAND2_X1 is_buffer = 0
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NAND2_X1 is_inverter = 0
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DFF_X1 is_leaf = 1
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DFF_X1 is_buffer = 0
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DFF_X1 is_inverter = 0
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INV_X1 lib name = NangateOpenCellLibrary
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SDFF_X1 has test_cell
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INV_X1/A function =
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INV_X1/ZN function = !A
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TINV_X1/EN function =
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TINV_X1/ZN tristate_enable = !EN
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INV_X1/A bus_name = A
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INV_X1/A is_bus = 0
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INV_X1/A is_bus_bit = 0
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INV_X1/A is_bundle = 0
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INV_X1/A is_bundle_member = 0
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INV_X1/A has_members = 0
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INV_X1/A is_pwr_gnd = 0
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INV_X1/A scan_signal_type = none
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SDFF_X1/SI scan_signal_type = none
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SDFF_X1/SI is_bus = 0
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INV_X1 all ports = 4
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NAND2_X1 A* ports = 2
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NAND2_X1 regexp ports = 2
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NAND2_X1 nocase zn ports = 0
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INV_X1 ports via iterator = 4
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AOI21_X1 ports via iterator = 6
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Arc: INV_X1 A -> ZN role=combinational is_check=0
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sdf_cond=
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DFF Arc: DFF_X1 CK -> D role=hold is_check=1
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DFF Arc: DFF_X1 CK -> D role=setup is_check=1
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DFF Arc: DFF_X1 CK -> CK role=width is_check=1
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DFF Arc: DFF_X1 CK -> Q role=Reg Clk to Q is_check=0
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DFF Arc: DFF_X1 CK -> QN role=Reg Clk to Q is_check=0
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DFFR Arc: DFFR_X1 CK -> D role=hold is_check=1
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DFFR Arc: DFFR_X1 CK -> D role=setup is_check=1
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DFFR Arc: DFFR_X1 CK -> RN role=recovery is_check=1
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DFFR Arc: DFFR_X1 CK -> RN role=removal is_check=1
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DFFR Arc: DFFR_X1 RN -> RN role=width is_check=1
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DFFR Arc: DFFR_X1 CK -> CK role=width is_check=1
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DFFR Arc: DFFR_X1 CK -> Q role=Reg Clk to Q is_check=0
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DFFR Arc: DFFR_X1 RN -> Q role=Reg Set/Clr is_check=0
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DFFR Arc: DFFR_X1 RN -> Q role=Reg Set/Clr is_check=0
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DFFR Arc: DFFR_X1 RN -> Q role=Reg Set/Clr is_check=0
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DFFR Arc: DFFR_X1 RN -> Q role=Reg Set/Clr is_check=0
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DFFR Arc: DFFR_X1 CK -> QN role=Reg Clk to Q is_check=0
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DFFR Arc: DFFR_X1 RN -> QN role=Reg Set/Clr is_check=0
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DFFR Arc: DFFR_X1 RN -> QN role=Reg Set/Clr is_check=0
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DFFR Arc: DFFR_X1 RN -> QN role=Reg Set/Clr is_check=0
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DFFR Arc: DFFR_X1 RN -> QN role=Reg Set/Clr is_check=0
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Arc detail: A rise -> ZN fall role=combinational
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Arc detail: A fall -> ZN rise role=combinational
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DFF arc: rise -> rise role=hold
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DFF arc: rise -> fall role=hold
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DFF arc: rise -> rise role=setup
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DFF arc: rise -> fall role=setup
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DFF arc: rise -> fall role=width
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DFF arc: fall -> rise role=width
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DFF arc: rise -> rise role=Reg Clk to Q
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DFF arc: rise -> fall role=Reg Clk to Q
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DFF arc: rise -> rise role=Reg Clk to Q
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DFF arc: rise -> fall role=Reg Clk to Q
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Default opcond process = 1.0
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Default opcond voltage = 1.100000023841858
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Default opcond temperature = 25.0
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Typical opcond process = 1.0
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Typical opcond voltage = 1.100000023841858
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Typical opcond temperature = 25.0
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Found wireload 5K_hvratio_1_1
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Found wireload selection
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Library: NangateOpenCellLibrary
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INV_X1/A cap max = 1.700229965024007e-15
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INV_X1/A cap min = 1.5493600563490969e-15
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PwrGnd port: VDD dir=power
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PwrGnd port: VSS dir=ground
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FA_X1 port: VDD dir=power is_bus=0
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FA_X1 port: VSS dir=ground is_bus=0
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FA_X1 port: A dir=input is_bus=0
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FA_X1 port: B dir=input is_bus=0
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FA_X1 port: CI dir=input is_bus=0
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FA_X1 port: CO dir=output is_bus=0
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FA_X1 port: S dir=output is_bus=0
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