34 lines
1.1 KiB
Plaintext
34 lines
1.1 KiB
Plaintext
--- report_checks baseline ---
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Startpoint: in1 (input port clocked by clk)
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Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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1.00 1.00 v input external delay
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0.00 1.00 v in1 (in)
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0.06 1.06 v buf1/Z (BUF_X1)
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0.00 1.06 v reg1/D (DFF_X1)
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1.06 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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10.00 ^ reg1/CK (DFF_X1)
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-0.04 9.96 library setup time
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9.96 data required time
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---------------------------------------------------------
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9.96 data required time
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-1.06 data arrival time
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---------------------------------------------------------
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8.90 slack (MET)
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--- write_path_spice max slack ---
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--- write_path_spice min path ---
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--- write_path_spice hspice ---
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--- write_path_spice xyce ---
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