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OpenSTA/sdc/test/sdc_derate_disable_deep.ok

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PASS: setup
PASS: global derate
PASS: global derate clock/data
PASS: global derate by type
PASS: global derate by type/clock_data/rf
Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk1)
Endpoint: out1 (output port clocked by clk1)
Path Group: clk1
Path Type: max
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk1 (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 ^ reg2/CK (DFF_X1)
0.08 0.08 ^ reg2/Q (DFF_X1)
0.00 0.08 ^ out1 (out)
0.08 data arrival time
10.00 10.00 clock clk1 (rise edge)
0.00 10.00 clock network delay (ideal)
0.00 10.00 clock reconvergence pessimism
-3.00 7.00 output external delay
7.00 data required time
---------------------------------------------------------
7.00 data required time
-0.08 data arrival time
---------------------------------------------------------
6.92 slack (MET)
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk1)
Endpoint: reg3 (rising edge-triggered flip-flop clocked by clk2)
Path Group: clk2
Path Type: max
Delay Time Description
---------------------------------------------------------
10.00 10.00 clock clk1 (rise edge)
0.00 10.00 clock network delay (ideal)
0.00 10.00 ^ reg1/CK (DFF_X1)
0.08 10.08 v reg1/Q (DFF_X1)
0.00 10.08 v reg3/D (DFF_X1)
10.08 data arrival time
20.00 20.00 clock clk2 (rise edge)
0.00 20.00 clock network delay (ideal)
0.00 20.00 clock reconvergence pessimism
20.00 ^ reg3/CK (DFF_X1)
-0.04 19.96 library setup time
19.96 data required time
---------------------------------------------------------
19.96 data required time
-10.08 data arrival time
---------------------------------------------------------
9.88 slack (MET)
PASS: report after global derate
PASS: lib cell derate
PASS: instance derate
PASS: net derate
Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk1)
Endpoint: out1 (output port clocked by clk1)
Path Group: clk1
Path Type: max
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk1 (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 ^ reg2/CK (DFF_X1)
0.08 0.08 ^ reg2/Q (DFF_X1)
0.00 0.08 ^ out1 (out)
0.08 data arrival time
10.00 10.00 clock clk1 (rise edge)
0.00 10.00 clock network delay (ideal)
0.00 10.00 clock reconvergence pessimism
-3.00 7.00 output external delay
7.00 data required time
---------------------------------------------------------
7.00 data required time
-0.08 data arrival time
---------------------------------------------------------
6.92 slack (MET)
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk1)
Endpoint: reg3 (rising edge-triggered flip-flop clocked by clk2)
Path Group: clk2
Path Type: max
Delay Time Description
---------------------------------------------------------
10.00 10.00 clock clk1 (rise edge)
0.00 10.00 clock network delay (ideal)
0.00 10.00 ^ reg1/CK (DFF_X1)
0.08 10.08 v reg1/Q (DFF_X1)
0.00 10.08 v reg3/D (DFF_X1)
10.08 data arrival time
20.00 20.00 clock clk2 (rise edge)
0.00 20.00 clock network delay (ideal)
0.00 20.00 clock reconvergence pessimism
20.00 ^ reg3/CK (DFF_X1)
-0.04 19.96 library setup time
19.96 data required time
---------------------------------------------------------
19.96 data required time
-10.08 data arrival time
---------------------------------------------------------
9.88 slack (MET)
PASS: report after all derates
PASS: write_sdc with derates
PASS: unset_timing_derate
PASS: disable lib cell all
PASS: disable lib cell from
PASS: disable lib cell to
PASS: disable lib cell from/to
PASS: disable lib cell from/to second
Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk1)
Endpoint: out1 (output port clocked by clk1)
Path Group: clk1
Path Type: max
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk1 (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 ^ reg2/CK (DFF_X1)
0.08 0.08 ^ reg2/Q (DFF_X1)
0.00 0.08 ^ out1 (out)
0.08 data arrival time
10.00 10.00 clock clk1 (rise edge)
0.00 10.00 clock network delay (ideal)
0.00 10.00 clock reconvergence pessimism
-3.00 7.00 output external delay
7.00 data required time
---------------------------------------------------------
7.00 data required time
-0.08 data arrival time
---------------------------------------------------------
6.92 slack (MET)
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk1)
Endpoint: reg3 (rising edge-triggered flip-flop clocked by clk2)
Path Group: clk2
Path Type: max
Delay Time Description
---------------------------------------------------------
10.00 10.00 clock clk1 (rise edge)
0.00 10.00 clock network delay (ideal)
0.00 10.00 ^ reg1/CK (DFF_X1)
0.08 10.08 v reg1/Q (DFF_X1)
0.00 10.08 v reg3/D (DFF_X1)
10.08 data arrival time
20.00 20.00 clock clk2 (rise edge)
0.00 20.00 clock network delay (ideal)
0.00 20.00 clock reconvergence pessimism
20.00 ^ reg3/CK (DFF_X1)
-0.04 19.96 library setup time
19.96 data required time
---------------------------------------------------------
19.96 data required time
-10.08 data arrival time
---------------------------------------------------------
9.88 slack (MET)
PASS: report after lib cell disables
PASS: disable instance all
PASS: disable instance from/to
PASS: disable instance from
PASS: disable instance to
Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk1)
Endpoint: out1 (output port clocked by clk1)
Path Group: clk1
Path Type: max
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk1 (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 ^ reg2/CK (DFF_X1)
0.08 0.08 ^ reg2/Q (DFF_X1)
0.00 0.08 ^ out1 (out)
0.08 data arrival time
10.00 10.00 clock clk1 (rise edge)
0.00 10.00 clock network delay (ideal)
0.00 10.00 clock reconvergence pessimism
-3.00 7.00 output external delay
7.00 data required time
---------------------------------------------------------
7.00 data required time
-0.08 data arrival time
---------------------------------------------------------
6.92 slack (MET)
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk1)
Endpoint: reg3 (rising edge-triggered flip-flop clocked by clk2)
Path Group: clk2
Path Type: max
Delay Time Description
---------------------------------------------------------
10.00 10.00 clock clk1 (rise edge)
0.00 10.00 clock network delay (ideal)
0.00 10.00 ^ reg1/CK (DFF_X1)
0.08 10.08 ^ reg1/Q (DFF_X1)
0.00 10.08 ^ reg3/D (DFF_X1)
10.08 data arrival time
20.00 20.00 clock clk2 (rise edge)
0.00 20.00 clock network delay (ideal)
0.00 20.00 clock reconvergence pessimism
20.00 ^ reg3/CK (DFF_X1)
-4242780356595809627609759744.00 -4242780356595809627609759744.00 library setup time
-4242780356595809627609759744.00 data required time
---------------------------------------------------------
-4242780356595809627609759744.00 data required time
-10.08 data arrival time
---------------------------------------------------------
-4242780356595809627609759744.00 slack (VIOLATED)
PASS: report after instance disables
PASS: disable pin
PASS: disable port
PASS: write_sdc with disables
PASS: write_sdc compatible with disables
PASS: unset lib cell disables
PASS: unset instance disables
PASS: unset pin disable
Warning: sdc_derate_disable_deep.tcl line 1, object 'sdc_test2' not found.
Warning: sdc_derate_disable_deep.tcl line 1, object 'sdc_test2' not found.
PASS: clock_gating_check global
PASS: clock_gating_check clock
PASS: clock_gating_check instance
PASS: clock_gating_check pin
disabled_edges_sorted count = 1
PASS: disabled_edges_sorted
PASS: final write_sdc
Startpoint: in2 (input port clocked by clk1)
Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk1)
Path Group: clk1
Path Type: max
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk1 (rise edge)
0.00 0.00 clock network delay (ideal)
2.00 2.00 ^ input external delay
0.00 2.00 ^ in2 (in)
0.00 2.00 v inv1/ZN (INV_X1)
0.03 2.03 v and1/ZN (AND2_X1)
0.01 2.05 ^ nand1/ZN (NAND2_X1)
0.00 2.05 ^ reg1/D (DFF_X1)
2.05 data arrival time
10.00 10.00 clock clk1 (rise edge)
0.00 10.00 clock network delay (ideal)
0.00 10.00 clock reconvergence pessimism
10.00 ^ reg1/CK (DFF_X1)
-4280578177924698267900182528.00 -4280578177924698267900182528.00 library setup time
-4280578177924698267900182528.00 data required time
---------------------------------------------------------
-4280578177924698267900182528.00 data required time
-2.05 data arrival time
---------------------------------------------------------
-4280578177924698267900182528.00 slack (VIOLATED)
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk1)
Endpoint: reg3 (rising edge-triggered flip-flop clocked by clk2)
Path Group: clk2
Path Type: max
Delay Time Description
---------------------------------------------------------
10.00 10.00 clock clk1 (rise edge)
0.00 10.00 clock network delay (ideal)
0.00 10.00 ^ reg1/CK (DFF_X1)
0.08 10.08 v reg1/Q (DFF_X1)
0.00 10.08 v reg3/D (DFF_X1)
10.08 data arrival time
20.00 20.00 clock clk2 (rise edge)
0.00 20.00 clock network delay (ideal)
0.00 20.00 clock reconvergence pessimism
20.00 ^ reg3/CK (DFF_X1)
-0.04 19.96 library setup time
19.96 data required time
---------------------------------------------------------
19.96 data required time
-10.08 data arrival time
---------------------------------------------------------
9.88 slack (MET)
PASS: final report
ALL PASSED
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