270 lines
7.9 KiB
Plaintext
270 lines
7.9 KiB
Plaintext
Startpoint: in1 (input port clocked by clk)
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Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 v input external delay
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0.00 0.00 v in1 (in)
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0.06 0.06 v buf1/Z (BUF_X1)
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0.03 0.08 v and1/ZN (AND2_X1)
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0.00 0.08 v reg1/D (DFF_X1)
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0.08 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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10.00 ^ reg1/CK (DFF_X1)
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-0.04 9.96 library setup time
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9.96 data required time
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---------------------------------------------------------
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9.96 data required time
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-0.08 data arrival time
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---------------------------------------------------------
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9.88 slack (MET)
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PASS: initial design
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--- connected pin queries ---
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Net n1
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Pin capacitance: 0.87-0.92
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Wire capacitance: 0.00
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Total capacitance: 0.87-0.92
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Number of drivers: 1
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Number of loads: 1
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Number of pins: 2
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Driver pins
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buf1/Z output (BUF_X1)
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Load pins
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and1/A1 input (AND2_X1) 0.87-0.92
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PASS: report_net n1
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Net n2
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Pin capacitance: 1.06-1.14
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Wire capacitance: 0.00
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Total capacitance: 1.06-1.14
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Number of drivers: 1
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Number of loads: 1
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Number of pins: 2
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Driver pins
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and1/ZN output (AND2_X1)
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Load pins
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reg1/D input (DFF_X1) 1.06-1.14
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PASS: report_net n2
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net n1 pins: 2
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net n2 pins: 2
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PASS: connected pin queries
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--- instance/connection lifecycle ---
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created 9 instances
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created 6 nets
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connect lifecycle_inst_0/A: 1
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connect lifecycle_inst_0/Z: 1
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connect lifecycle_inst_3/A: 1
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connect lifecycle_inst_3/ZN: 1
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Net lifecycle_net_1
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Pin capacitance: 1.55-1.70
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Wire capacitance: 0.00
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Total capacitance: 1.55-1.70
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Number of drivers: 1
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Number of loads: 1
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Number of pins: 2
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Driver pins
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lifecycle_inst_0/Z output (BUF_X1)
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Load pins
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lifecycle_inst_3/A input (INV_X1) 1.55-1.70
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report_net lifecycle_net_1: done
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replace BUF_X1->BUF_X2: ref=BUF_X2
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replace back BUF_X2->BUF_X1: ref=BUF_X1
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replace BUF_X1->BUF_X4: ref=BUF_X4
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Startpoint: in1 (input port clocked by clk)
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Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 v input external delay
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0.00 0.00 v in1 (in)
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0.06 0.06 v buf1/Z (BUF_X1)
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0.03 0.08 v and1/ZN (AND2_X1)
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0.00 0.08 v reg1/D (DFF_X1)
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0.08 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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10.00 ^ reg1/CK (DFF_X1)
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-0.04 9.96 library setup time
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9.96 data required time
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---------------------------------------------------------
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9.96 data required time
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-0.08 data arrival time
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---------------------------------------------------------
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9.88 slack (MET)
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PASS: timing after modifications
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--- disconnect and delete ---
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PASS: all pins disconnected
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PASS: all lifecycle instances deleted
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PASS: all lifecycle nets deleted
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final cells: 3
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Startpoint: in1 (input port clocked by clk)
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Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 v input external delay
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0.00 0.00 v in1 (in)
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0.06 0.06 v buf1/Z (BUF_X1)
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0.03 0.08 v and1/ZN (AND2_X1)
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0.00 0.08 v reg1/D (DFF_X1)
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0.08 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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10.00 ^ reg1/CK (DFF_X1)
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-0.04 9.96 library setup time
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9.96 data required time
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---------------------------------------------------------
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9.96 data required time
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-0.08 data arrival time
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---------------------------------------------------------
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9.88 slack (MET)
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PASS: timing after cleanup
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--- property queries ---
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clk: dir=input full_name=clk
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in1: dir=input full_name=in1
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in2: dir=input full_name=in2
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out1: dir=output full_name=out1
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buf1: ref=BUF_X1 full_name=buf1
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and1: ref=AND2_X1 full_name=and1
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reg1: ref=DFF_X1 full_name=reg1
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buf1/A: dir=input
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buf1/Z: dir=output
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and1/A1: dir=input
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and1/A2: dir=input
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and1/ZN: dir=output
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reg1/D: dir=input
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reg1/CK: dir=input
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reg1/Q: dir=output
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PASS: property queries
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--- replace_cell original instances ---
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and1 -> AND2_X2: AND2_X2
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Startpoint: in1 (input port clocked by clk)
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Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 v input external delay
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0.00 0.00 v in1 (in)
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0.06 0.06 v buf1/Z (BUF_X1)
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0.02 0.08 v and1/ZN (AND2_X2)
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0.00 0.08 v reg1/D (DFF_X1)
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0.08 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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10.00 ^ reg1/CK (DFF_X1)
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-0.04 9.96 library setup time
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9.96 data required time
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---------------------------------------------------------
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9.96 data required time
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-0.08 data arrival time
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---------------------------------------------------------
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9.88 slack (MET)
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PASS: timing after and1 replace
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Startpoint: in1 (input port clocked by clk)
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Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 v input external delay
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0.00 0.00 v in1 (in)
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0.06 0.06 v buf1/Z (BUF_X1)
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0.03 0.08 v and1/ZN (AND2_X1)
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0.00 0.08 v reg1/D (DFF_X1)
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0.08 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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10.00 ^ reg1/CK (DFF_X1)
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-0.04 9.96 library setup time
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9.96 data required time
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---------------------------------------------------------
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9.96 data required time
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-0.08 data arrival time
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---------------------------------------------------------
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9.88 slack (MET)
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PASS: timing after and1 restore
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buf1 -> BUF_X2: BUF_X2
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buf1 -> BUF_X4: BUF_X4
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buf1 -> BUF_X8: BUF_X8
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buf1 -> BUF_X16: BUF_X16
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buf1 -> BUF_X32: BUF_X32
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Startpoint: in1 (input port clocked by clk)
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Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 v input external delay
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0.00 0.00 v in1 (in)
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0.06 0.06 v buf1/Z (BUF_X1)
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0.03 0.08 v and1/ZN (AND2_X1)
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0.00 0.08 v reg1/D (DFF_X1)
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0.08 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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10.00 ^ reg1/CK (DFF_X1)
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-0.04 9.96 library setup time
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9.96 data required time
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---------------------------------------------------------
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9.96 data required time
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-0.08 data arrival time
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---------------------------------------------------------
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9.88 slack (MET)
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PASS: buf1 multi-replace cycle
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ALL PASSED
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