30 lines
1.1 KiB
Tcl
30 lines
1.1 KiB
Tcl
# Test SPEF read and parasitics reporting
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# reg1_asap7 uses ASAP7 cells
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read_liberty ../../test/asap7/asap7sc7p5t_SEQ_RVT_FF_nldm_220123.lib
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read_liberty ../../test/asap7/asap7sc7p5t_INVBUF_RVT_FF_nldm_220122.lib.gz
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read_liberty ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz
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read_liberty ../../test/asap7/asap7sc7p5t_OA_RVT_FF_nldm_211120.lib.gz
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read_liberty ../../test/asap7/asap7sc7p5t_AO_RVT_FF_nldm_211120.lib.gz
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read_verilog ../../test/reg1_asap7.v
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link_design top
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create_clock -name clk1 -period 10 [get_ports clk1]
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# Read SPEF
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read_spef ../../test/reg1_asap7.spef
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set corner [sta::cmd_scene]
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foreach net_name {r1q r2q u1z u2z} {
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set net [get_nets $net_name]
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set total_cap [$net capacitance $corner "max"]
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set pin_cap [$net pin_capacitance $corner "max"]
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set wire_cap [$net wire_capacitance $corner "max"]
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puts "$net_name total_cap=$total_cap pin_cap=$pin_cap wire_cap=$wire_cap"
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if {$total_cap <= 0.0} {
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error "expected positive capacitance on net $net_name after SPEF read"
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}
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}
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report_checks -fields {slew cap input_pins fanout}
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