143 lines
5.5 KiB
Tcl
143 lines
5.5 KiB
Tcl
# Test Levelize.cc: levelization with disabled arcs, loop detection,
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# re-levelization after constraint changes, and level query operations.
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# Uses search_check_timing.v (has multiple clocks).
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# Targets: Levelize.cc levelize, ensureLevelized,
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# levelizeFrom, isDisabledLoop, checkLoops, reportLoops,
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# relevelize, clearLogicValues, graphChangedAfterLevelize,
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# Search.cc levelize, levelizeGraph, reportLoops
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source ../../test/helpers.tcl
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read_liberty ../../test/nangate45/Nangate45_typ.lib
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read_verilog search_check_timing.v
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link_design search_check_timing
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create_clock -name clk -period 10 [get_ports clk]
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create_clock -name clk2 -period 15 [get_ports clk2]
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set_input_delay -clock clk 1.0 [get_ports in1]
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set_input_delay -clock clk 1.0 [get_ports in2]
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set_input_delay -clock clk 1.0 [get_ports in3]
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set_input_delay -clock clk 0.5 [get_ports in_unconst]
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set_output_delay -clock clk 2.0 [get_ports out1]
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set_output_delay -clock clk2 3.0 [get_ports out2]
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# Run initial timing (triggers levelize)
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puts "--- initial timing ---"
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report_checks -path_delay max
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report_checks -path_delay min
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############################################################
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# Disable timing arcs and re-run (triggers re-levelize)
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############################################################
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puts "--- disable_timing ---"
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set_disable_timing [get_cells buf1] -from A -to Z
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report_checks -path_delay max
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puts "--- enable_timing ---"
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unset_disable_timing [get_cells buf1] -from A -to Z
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report_checks -path_delay max
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############################################################
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# set_disable_timing on lib cell arcs
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############################################################
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puts "--- disable lib cell arcs ---"
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set_disable_timing [get_lib_cells Nangate45/AND2_X1] -from A1 -to ZN
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report_checks -path_delay max
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puts "--- re-enable lib cell arcs ---"
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unset_disable_timing [get_lib_cells Nangate45/AND2_X1] -from A1 -to ZN
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report_checks -path_delay max
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############################################################
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# set_case_analysis (can cause logic constant propagation
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# which triggers levelize through sim values)
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############################################################
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puts "--- set_case_analysis ---"
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set_case_analysis 1 [get_ports in2]
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report_checks -path_delay max
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puts "--- remove case_analysis ---"
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unset_case_analysis [get_ports in2]
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report_checks -path_delay max
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############################################################
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# check_setup to report unconstrained endpoints
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############################################################
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puts "--- check_setup ---"
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check_setup -verbose
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############################################################
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# report_disabled_edges
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############################################################
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puts "--- report_disabled_edges ---"
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report_disabled_edges
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############################################################
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# Timing with different clock uncertainties (triggers
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# re-search which exercises levelize + tag operations)
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############################################################
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puts "--- inter-clock uncertainty ---"
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set_clock_uncertainty -setup 0.5 -from [get_clocks clk] -to [get_clocks clk2]
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set_clock_uncertainty -hold 0.2 -from [get_clocks clk] -to [get_clocks clk2]
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report_checks -path_delay max
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report_checks -path_delay min
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############################################################
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# Disable whole instance (all arcs)
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############################################################
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puts "--- disable_timing whole instance ---"
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set_disable_timing [get_cells and1]
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report_checks -path_delay max
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puts "--- enable_timing whole instance ---"
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unset_disable_timing [get_cells and1]
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report_checks -path_delay max
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############################################################
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# check_setup with loop detection
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############################################################
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puts "--- check_setup -loops ---"
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check_setup -verbose -loops
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############################################################
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# Multiple timing operations that force re-levelize
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############################################################
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puts "--- multiple re-levelize triggers ---"
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set_false_path -from [get_ports in1] -to [get_pins reg1/D]
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report_checks -path_delay max
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unset_path_exceptions -from [get_ports in1] -to [get_pins reg1/D]
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report_checks -path_delay max
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set_multicycle_path 2 -setup -from [get_clocks clk] -to [get_clocks clk2]
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report_checks -path_delay max
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############################################################
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# Disable timing on ports
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############################################################
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puts "--- disable timing on port ---"
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set_disable_timing [get_ports in1]
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report_checks -path_delay max
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puts "--- enable timing on port ---"
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unset_disable_timing [get_ports in1]
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report_checks -path_delay max
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############################################################
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# set_case_analysis 0 (different constant)
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############################################################
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puts "--- set_case_analysis 0 ---"
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set_case_analysis 0 [get_ports in1]
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report_checks -path_delay max
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puts "--- remove case_analysis 0 ---"
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unset_case_analysis [get_ports in1]
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report_checks -path_delay max
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############################################################
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# Multiple clock domains with different constraints
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############################################################
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puts "--- add constraints and re-analyze ---"
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set_clock_latency -source 0.3 [get_clocks clk]
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set_clock_latency -source 0.5 [get_clocks clk2]
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set_clock_transition 0.1 [get_clocks clk]
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report_checks -path_delay max -format full_clock_expanded
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report_checks -path_delay min -format full_clock_expanded
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