205 lines
7.0 KiB
Tcl
205 lines
7.0 KiB
Tcl
# Test comprehensive write_sdc for WriteSdc.cc code coverage
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# Also exercises many Sdc.cc, Clock.cc, ExceptionPath.cc paths
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source ../../test/helpers.tcl
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read_liberty ../../test/nangate45/Nangate45_typ.lib
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read_verilog sdc_test2.v
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link_design sdc_test2
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############################################################
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# Create multiple clocks with various options
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############################################################
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# Basic clocks
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create_clock -name clk1 -period 10 [get_ports clk1]
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create_clock -name clk2 -period 20 -waveform {0 10} [get_ports clk2]
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create_clock -name vclk -period 5
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create_clock -name clk1_fast -period 5 -add [get_ports clk1]
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# Generated clock
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create_generated_clock -name gen_div2 -source [get_ports clk1] -divide_by 2 [get_pins reg1/Q]
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create_generated_clock -name gen_mul3 -source [get_ports clk2] -multiply_by 3 [get_pins reg3/Q]
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# Propagated clock
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set_propagated_clock [get_clocks clk1]
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############################################################
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# Clock constraints
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############################################################
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# Clock latency (source and network)
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set_clock_latency -source 0.5 [get_clocks clk1]
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set_clock_latency -source -rise -max 0.6 [get_clocks clk1]
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set_clock_latency -source -fall -min 0.3 [get_clocks clk1]
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set_clock_latency 0.2 [get_clocks clk2]
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set_clock_latency -rise -max 0.4 [get_clocks clk2]
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set_clock_latency -fall -min 0.1 [get_clocks clk2]
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# Clock uncertainty (simple and inter-clock)
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set_clock_uncertainty -setup 0.2 [get_clocks clk1]
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set_clock_uncertainty -hold 0.1 [get_clocks clk1]
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set_clock_uncertainty -from [get_clocks clk1] -to [get_clocks clk2] -setup 0.3
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set_clock_uncertainty -from [get_clocks clk1] -to [get_clocks clk2] -hold 0.15
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# Clock transition
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set_clock_transition -rise -max 0.15 [get_clocks clk1]
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set_clock_transition -fall -min 0.08 [get_clocks clk1]
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set_clock_transition 0.1 [get_clocks clk2]
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############################################################
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# IO constraints
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############################################################
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# Input delays with various options
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set_input_delay -clock clk1 2.0 [get_ports in1]
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set_input_delay -clock clk1 -rise -max 2.5 [get_ports in2]
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set_input_delay -clock clk1 -fall -min 1.0 [get_ports in2]
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set_input_delay -clock clk2 1.8 [get_ports in3]
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set_input_delay -clock clk1 -clock_fall 1.5 [get_ports in3] -add_delay
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# Output delays with various options
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set_output_delay -clock clk1 3.0 [get_ports out1]
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set_output_delay -clock clk2 -rise -max 3.5 [get_ports out2]
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set_output_delay -clock clk2 -fall -min 1.5 [get_ports out2] -add_delay
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############################################################
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# Driving cell and load
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############################################################
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set_driving_cell -lib_cell BUF_X1 [get_ports in1]
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set_driving_cell -lib_cell INV_X1 -pin ZN [get_ports in2]
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set_driving_cell -lib_cell BUF_X4 [get_ports in3]
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# set_drive
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set_drive 100 [get_ports in1]
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set_load 0.05 [get_ports out1]
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set_load -pin_load 0.03 [get_ports out2]
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# Input transition
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set_input_transition 0.15 [get_ports in1]
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set_input_transition -rise -max 0.12 [get_ports in2]
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set_input_transition -fall -min 0.08 [get_ports in2]
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############################################################
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# Design limits
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############################################################
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set_max_transition 0.5 [current_design]
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set_max_capacitance 0.2 [current_design]
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set_max_fanout 20 [current_design]
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set_max_transition 0.3 [get_ports out1]
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set_max_capacitance 0.1 [get_ports out1]
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set_max_transition -clock_path 0.2 [get_clocks clk1]
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set_max_transition -data_path 0.4 [get_clocks clk1]
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############################################################
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# Exception paths
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############################################################
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# False path
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set_false_path -from [get_clocks clk1] -to [get_clocks clk2]
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set_false_path -from [get_ports in1] -through [get_pins and1/ZN] -to [get_ports out1]
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set_false_path -rise_from [get_ports in3] -fall_to [get_ports out2]
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# Multicycle path
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set_multicycle_path -setup 2 -from [get_ports in1] -to [get_ports out1]
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set_multicycle_path -hold 1 -from [get_ports in1] -to [get_ports out1]
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# Max/min delay
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set_max_delay -from [get_ports in2] -to [get_ports out1] 8.0
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set_min_delay -from [get_ports in2] -to [get_ports out1] 1.0
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# Group path
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group_path -name group_clk1 -from [get_clocks clk1]
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group_path -name group_io -from [get_ports in1] -to [get_ports out1]
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############################################################
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# Clock groups
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############################################################
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set_clock_groups -asynchronous -group {clk1 clk1_fast} -group {clk2}
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############################################################
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# Clock sense
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############################################################
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set_clock_sense -positive -clocks [get_clocks clk1] [get_pins buf1/Z]
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############################################################
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# Case analysis and logic values
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############################################################
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set_case_analysis 0 [get_ports in3]
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############################################################
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# Operating conditions
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############################################################
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set_operating_conditions typical
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############################################################
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# Wire load
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############################################################
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set_wire_load_model -name "5K_hvratio_1_1"
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set_wire_load_mode enclosed
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############################################################
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# Timing derate
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############################################################
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set_timing_derate -early 0.95
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set_timing_derate -late 1.05
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############################################################
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# Disable timing
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############################################################
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set_disable_timing [get_cells buf1]
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set_disable_timing [get_lib_cells NangateOpenCellLibrary/INV_X1] -from A -to ZN
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############################################################
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# Min pulse width
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############################################################
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set_min_pulse_width 1.0 [get_clocks clk1]
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############################################################
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# Port external pin cap
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############################################################
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set_port_fanout_number 4 [get_ports out1]
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############################################################
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# Resistance
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############################################################
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set_resistance -min 10.0 [get_nets n1]
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set_resistance -max 20.0 [get_nets n1]
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############################################################
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# set_max_area
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############################################################
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set_max_area 100.0
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############################################################
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# Write SDC with various options
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############################################################
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set sdc_file1 [make_result_file sdc_write_comprehensive1.sdc]
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write_sdc -no_timestamp $sdc_file1
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set sdc_file2 [make_result_file sdc_write_comprehensive2.sdc]
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write_sdc -no_timestamp -digits 6 $sdc_file2
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############################################################
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# Read back SDC
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############################################################
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# Read the SDC file (re-applying constraints)
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read_sdc $sdc_file1
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report_checks
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