191 lines
6.8 KiB
Tcl
191 lines
6.8 KiB
Tcl
# Test remove_clock, disable/remove clock gating check, capacitance limits
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# on cell/port/pin targets, and set_load with -corner variants.
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# Targets:
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# Sdc.cc: removeClock (full cascade: deleteExceptionsReferencing,
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# deleteInputDelaysReferencing, deleteOutputDelaysReferencing,
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# deleteClockLatenciesReferencing, deleteClockInsertionsReferencing,
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# deleteInterClockUncertaintiesReferencing, deleteLatchBorrowLimitsReferencing,
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# deleteMinPulseWidthReferencing, deleteMasterClkRefs, clockGroupsDeleteClkRefs),
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# disableClockGatingCheck(Instance), disableClockGatingCheck(Pin),
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# removeDisableClockGatingCheck(Instance), removeDisableClockGatingCheck(Pin),
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# isDisableClockGatingCheck(Instance), isDisableClockGatingCheck(Pin),
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# setCapacitanceLimit(Cell/Port/Pin), capacitanceLimit(Port/Pin),
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# isLeafPinClock, portExtCap (various overloads),
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# hasPortExtCap, portExtFanout, ensurePortExtPinCap
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# WriteSdc.cc: writePortLoads, writePortExtCap, writeClockGatingCheck,
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# writeMinPulseWidths, writeInterClockUncertainty
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# Clock.cc: removeClock triggers clock deletion and re-creation
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source ../../test/helpers.tcl
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read_liberty ../../test/nangate45/Nangate45_typ.lib
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read_verilog sdc_test2.v
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link_design sdc_test2
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############################################################
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# Phase 1: Build full constraint environment referencing clocks
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############################################################
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create_clock -name clk1 -period 10 [get_ports clk1]
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create_clock -name clk2 -period 20 -waveform {0 10} [get_ports clk2]
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create_clock -name vclk -period 5
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# Generated clocks referencing master clocks
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create_generated_clock -name gclk1 -source [get_ports clk1] -divide_by 2 [get_pins reg1/Q]
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create_generated_clock -name gclk2 -source [get_ports clk2] -multiply_by 3 [get_pins reg3/Q]
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# IO delays referencing clk1 and clk2
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set_input_delay -clock clk1 2.0 [get_ports in1]
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set_input_delay -clock clk1 2.5 [get_ports in2]
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set_input_delay -clock clk2 1.8 [get_ports in3]
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set_output_delay -clock clk1 3.0 [get_ports out1]
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set_output_delay -clock clk2 3.5 [get_ports out2]
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# Clock latency referencing clk1
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set_clock_latency -source 0.5 [get_clocks clk1]
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set_clock_latency -source -early 0.3 [get_clocks clk1]
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set_clock_latency -source -late 0.6 [get_clocks clk1]
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set_clock_latency 0.2 [get_clocks clk2]
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# Clock insertion
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set_clock_latency -source -rise -early 0.25 [get_clocks clk1]
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set_clock_latency -source -fall -late 0.55 [get_clocks clk1]
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# Inter-clock uncertainty referencing clk1-clk2
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set_clock_uncertainty -from [get_clocks clk1] -to [get_clocks clk2] -setup 0.3
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set_clock_uncertainty -from [get_clocks clk1] -to [get_clocks clk2] -hold 0.15
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set_clock_uncertainty -from [get_clocks clk2] -to [get_clocks clk1] -setup 0.28
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set_clock_uncertainty -from [get_clocks clk2] -to [get_clocks clk1] -hold 0.12
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set_clock_uncertainty -setup 0.2 [get_clocks clk1]
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set_clock_uncertainty -hold 0.1 [get_clocks clk1]
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# Latch borrow limits referencing clk1
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set_max_time_borrow 2.0 [get_clocks clk1]
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set_max_time_borrow 1.5 [get_clocks clk2]
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set_max_time_borrow 1.0 [get_pins reg1/D]
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# Min pulse width referencing clk1
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set_min_pulse_width -high 0.6 [get_clocks clk1]
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set_min_pulse_width -low 0.4 [get_clocks clk1]
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set_min_pulse_width 0.8 [get_clocks clk2]
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# Clock groups referencing clk1
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set_clock_groups -asynchronous -name async1 \
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-group {clk1 gclk1} \
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-group {clk2 gclk2}
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# Exception paths referencing clk1
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set_false_path -from [get_clocks clk1] -to [get_clocks clk2]
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set_multicycle_path -setup 2 -from [get_ports in1] -to [get_ports out1]
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# Write before deletion
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set sdc1 [make_result_file sdc_rmclk1.sdc]
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write_sdc -no_timestamp $sdc1
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report_checks
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############################################################
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# Phase 2: Clock gating check - disable on instance and pin
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############################################################
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# Design-level clock gating check
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set_clock_gating_check -setup 0.5 [current_design]
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set_clock_gating_check -hold 0.3 [current_design]
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# Clock-level
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set_clock_gating_check -setup 0.4 [get_clocks clk1]
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set_clock_gating_check -hold 0.2 [get_clocks clk1]
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# Instance-level
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set_clock_gating_check -setup 0.3 [get_cells reg1]
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set_clock_gating_check -hold 0.1 [get_cells reg1]
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# Pin-level
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set_clock_gating_check -setup 0.25 [get_pins reg1/CK]
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set_clock_gating_check -hold 0.08 [get_pins reg1/CK]
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# Write with clock gating
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set sdc2 [make_result_file sdc_rmclk2.sdc]
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write_sdc -no_timestamp $sdc2
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############################################################
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# Phase 3: Capacitance limits on cell, port, pin
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############################################################
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# Port capacitance limit
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set_max_capacitance 0.15 [get_ports out1]
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set_max_capacitance 0.20 [get_ports out2]
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set_min_capacitance 0.01 [get_ports out1]
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# Pin capacitance limit
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set_max_capacitance 0.10 [get_pins reg1/D]
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# Cell capacitance limit (via design)
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set_max_capacitance 0.25 [current_design]
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############################################################
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# Phase 4: set_load with various options for portExtCap
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############################################################
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# Basic pin load
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set_load -pin_load 0.05 [get_ports out1]
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set_load -wire_load 0.02 [get_ports out1]
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# Rise/fall loads
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set_load -pin_load -rise 0.04 [get_ports out2]
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set_load -pin_load -fall 0.045 [get_ports out2]
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# Min/max loads
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set_load -min 0.01 [get_ports out1]
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set_load -max 0.06 [get_ports out1]
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# Port fanout
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set_port_fanout_number 4 [get_ports out1]
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set_port_fanout_number 8 [get_ports out2]
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# Write with loads
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set sdc3 [make_result_file sdc_rmclk3.sdc]
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write_sdc -no_timestamp $sdc3
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set sdc3c [make_result_file sdc_rmclk3_compat.sdc]
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write_sdc -no_timestamp -compatible $sdc3c
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############################################################
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# Phase 5: Delete clocks (exercises removeClock cascade)
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############################################################
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# Delete generated clocks first (dependent on masters)
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delete_generated_clock [get_clocks gclk1]
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delete_generated_clock [get_clocks gclk2]
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# Delete virtual clock
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delete_clock [get_clocks vclk]
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# Delete master clock clk2 (removes IO delays, uncertainty, etc.)
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delete_clock [get_clocks clk2]
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report_clock_properties
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# Write after deletions - exercises writing with reduced constraints
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set sdc4 [make_result_file sdc_rmclk4.sdc]
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write_sdc -no_timestamp $sdc4
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report_checks
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############################################################
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# Phase 6: Re-create clocks and verify
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############################################################
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create_clock -name clk2_new -period 15 [get_ports clk2]
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set_input_delay -clock clk2_new 1.5 [get_ports in3]
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set_output_delay -clock clk2_new 2.5 [get_ports out2]
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set_clock_uncertainty -from [get_clocks clk1] -to [get_clocks clk2_new] -setup 0.25
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# Write final
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set sdc5 [make_result_file sdc_rmclk5.sdc]
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write_sdc -no_timestamp $sdc5
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# Read back and verify
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read_sdc $sdc5
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report_checks
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