193 lines
6.6 KiB
Tcl
193 lines
6.6 KiB
Tcl
# Test findCellsMatching with various regex/glob patterns across multiple
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# libraries, and exercise network property queries on matched cells.
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# Targets:
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# Network.cc: findCellsMatching (glob and regex modes, nocase),
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# findCell, findPort, findNet, findPin,
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# isDriver, isLoad, portDirection, isInput, isOutput,
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# pathName, shortPathName, cellName, portName
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# ConcreteNetwork.cc: findCell, findCellsMatching,
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# portBitCount, portCount, cellNetworkView, setCellNetworkView
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# PatternMatch.cc: glob matching, regex matching, nocase matching
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source ../../test/helpers.tcl
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############################################################
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# Read multiple libraries to have a rich cell database
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############################################################
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read_liberty ../../test/nangate45/Nangate45_typ.lib
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read_liberty ../../test/sky130hd/sky130hd_tt.lib
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read_liberty ../../test/asap7/asap7sc7p5t_INVBUF_RVT_FF_nldm_220122.lib.gz
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read_liberty ../../test/asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz
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read_liberty ../../test/asap7/asap7sc7p5t_SEQ_RVT_FF_nldm_220123.lib
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read_liberty ../../test/ihp-sg13g2/sg13g2_stdcell_typ_1p20V_25C.lib
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# Need a linked design for some operations
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read_verilog ../../examples/example1.v
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link_design top
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############################################################
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# Glob pattern matching across all libraries
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############################################################
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puts "--- glob matching ---"
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# Match all cells
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set all [sta::find_cells_matching "*" 0 0]
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puts "glob *: [llength $all] cells"
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# Match specific prefixes
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set inv_cells [sta::find_cells_matching "INV_*" 0 0]
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puts "glob INV_*: [llength $inv_cells] cells"
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set buf_cells [sta::find_cells_matching "BUF_*" 0 0]
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puts "glob BUF_*: [llength $buf_cells] cells"
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set dff_cells [sta::find_cells_matching "DFF*" 0 0]
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puts "glob DFF*: [llength $dff_cells] cells"
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set nand_cells [sta::find_cells_matching "*NAND*" 0 0]
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puts "glob *NAND*: [llength $nand_cells] cells"
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set nor_cells [sta::find_cells_matching "*NOR*" 0 0]
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puts "glob *NOR*: [llength $nor_cells] cells"
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# Sky130-specific patterns
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set sky_inv [sta::find_cells_matching "sky130_fd_sc_hd__inv_*" 0 0]
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puts "glob sky130 inv: [llength $sky_inv] cells"
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set sky_buf [sta::find_cells_matching "sky130_fd_sc_hd__buf_*" 0 0]
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puts "glob sky130 buf: [llength $sky_buf] cells"
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set sky_dff [sta::find_cells_matching "sky130_fd_sc_hd__dfxtp_*" 0 0]
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puts "glob sky130 dfxtp: [llength $sky_dff] cells"
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# ASAP7-specific patterns
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set asap7_inv [sta::find_cells_matching "INVx*_ASAP7_*" 0 0]
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puts "glob ASAP7 INV: [llength $asap7_inv] cells"
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set asap7_buf [sta::find_cells_matching "BUFx*_ASAP7_*" 0 0]
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puts "glob ASAP7 BUF: [llength $asap7_buf] cells"
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# IHP-specific patterns
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set ihp_inv [sta::find_cells_matching "sg13g2_inv_*" 0 0]
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puts "glob IHP inv: [llength $ihp_inv] cells"
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set ihp_buf [sta::find_cells_matching "sg13g2_buf_*" 0 0]
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puts "glob IHP buf: [llength $ihp_buf] cells"
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# No-match pattern
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set no_match [sta::find_cells_matching "NONEXISTENT_*" 0 0]
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puts "glob NONEXISTENT: [llength $no_match] cells"
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############################################################
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# Regex pattern matching
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############################################################
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puts "--- regex matching ---"
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# Simple regex
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set regex_inv [sta::find_cells_matching {^INV_X[0-9]+$} 1 0]
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puts "regex INV_Xn: [llength $regex_inv] cells"
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set regex_buf [sta::find_cells_matching {^BUF_X[0-9]+$} 1 0]
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puts "regex BUF_Xn: [llength $regex_buf] cells"
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set regex_nand [sta::find_cells_matching {^NAND[234]_X[0-9]+$} 1 0]
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puts "regex NANDn: [llength $regex_nand] cells"
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# More complex regex
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set regex_all_inv [sta::find_cells_matching ".*inv.*" 1 0]
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puts "regex .*inv.*: [llength $regex_all_inv] cells"
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set regex_all_dff [sta::find_cells_matching {.*[Dd][Ff][Ff].*} 1 0]
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puts "regex DFF: [llength $regex_all_dff] cells"
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# Sky130 regex
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set regex_sky_all [sta::find_cells_matching "^sky130_.*" 1 0]
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puts "regex sky130: [llength $regex_sky_all] cells"
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############################################################
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# Case-insensitive matching
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############################################################
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puts "--- nocase matching ---"
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set nocase_inv [sta::find_cells_matching "inv_*" 0 1]
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puts "nocase inv_*: [llength $nocase_inv] cells"
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set nocase_buf [sta::find_cells_matching "buf_*" 0 1]
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puts "nocase buf_*: [llength $nocase_buf] cells"
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set nocase_dff [sta::find_cells_matching "dff*" 0 1]
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puts "nocase dff*: [llength $nocase_dff] cells"
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############################################################
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# Liberty-level cell and port matching
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############################################################
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puts "--- liberty cell/port matching ---"
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set ng_lib [lindex [get_libs NangateOpenCellLibrary] 0]
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# Cell matching on specific library
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set lib_inv [sta::find_cells_matching "INV_*" 0 0]
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puts "lib INV: [llength $lib_inv]"
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# Find specific liberty cell
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set lc [sta::find_liberty_cell "NangateOpenCellLibrary/INV_X1"]
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if {$lc != "NULL"} {
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puts "find_liberty_cell: [$lc name]"
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}
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# Find liberty from name
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set found_lib [sta::find_liberty NangateOpenCellLibrary]
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puts "find_liberty: [$found_lib name]"
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set found_lib [sta::find_liberty sky130_fd_sc_hd__tt_025C_1v80]
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puts "find_liberty: [$found_lib name]"
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# Find liberty cell directly
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set asap7_cell [sta::find_liberty_cell "asap7sc7p5t_INVBUF_RVT_FF_nldm_211120/INVx1_ASAP7_75t_R"]
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if {$asap7_cell != "NULL"} {
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puts "ASAP7 find_liberty_cell: [$asap7_cell name]"
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}
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############################################################
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# Design-level queries after linking
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############################################################
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puts "--- design queries ---"
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# Find specific instances
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foreach inst_name {r1 r2 r3 u1 u2} {
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set inst [get_cells $inst_name]
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set ref [get_property $inst ref_name]
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set fn [get_full_name $inst]
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puts "$inst_name: ref=$ref fn=$fn"
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}
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# Find specific pins
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foreach pin_path {r1/D r1/CK r1/Q u1/A u1/Z u2/A1 u2/A2 u2/ZN} {
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set pin [get_pins $pin_path]
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set dir [get_property $pin direction]
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set fn [get_full_name $pin]
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puts "$pin_path: dir=$dir fn=$fn"
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}
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# Net driver/load queries
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foreach net_name {r1q r2q u1z u2z} {
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set net [get_nets $net_name]
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set pins [get_pins -of_objects $net]
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puts "net $net_name: [llength $pins] pins"
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}
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############################################################
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# Timing with the design
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############################################################
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puts "--- timing ---"
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create_clock -name clk -period 10 {clk1 clk2 clk3}
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set_input_delay -clock clk 0 {in1 in2}
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set_output_delay -clock clk 0 [get_ports out]
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set_input_transition 0.1 [all_inputs]
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report_checks -endpoint_count 3
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report_checks -path_delay min
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report_checks -from [get_ports in1] -to [get_ports out]
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report_checks -from [get_ports in2] -to [get_ports out]
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