222 lines
6.5 KiB
C++
222 lines
6.5 KiB
C++
// OpenSTA, Static Timing Analyzer
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// Copyright (c) 2020, Parallax Software, Inc.
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//
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <https://www.gnu.org/licenses/>.
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#pragma once
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#include <queue>
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#include <mutex>
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#include "StaConfig.hh" // CUDD
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#include "DisallowCopyAssign.hh"
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#include "Map.hh"
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#include "NetworkClass.hh"
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#include "GraphClass.hh"
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#include "SdcClass.hh"
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#include "StaState.hh"
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struct DdNode;
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struct DdManager;
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namespace sta {
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class SimObserver;
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typedef Map<const Pin*, LogicValue> PinValueMap;
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typedef std::queue<const Instance*> EvalQueue;
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typedef Map<const char*, DdNode*, CharPtrLess> BddSymbolTable;
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// Propagate constants from constraints and netlist tie high/low
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// connections thru gates.
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class Sim : public StaState
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{
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public:
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explicit Sim(StaState *sta);
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virtual ~Sim();
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void clear();
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// Set the observer for simulation value changes.
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void setObserver(SimObserver *observer);
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void ensureConstantsPropagated();
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void constantsInvalid();
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LogicValue evalExpr(const FuncExpr *expr,
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const Instance *inst) const;
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LogicValue logicValue(const Pin *pin) const;
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bool logicZeroOne(const Pin *pin) const;
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bool logicZeroOne(const Vertex *vertex) const;
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// Timing sense for the function between from_pin and to_pin
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// after simplifying the function based constants on the pins.
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virtual TimingSense functionSense(const Instance *inst,
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const Pin *from_pin,
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const Pin *to_pin);
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// Network edits.
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void deleteInstanceBefore(Instance *inst);
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void makePinAfter(Pin *pin);
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void deletePinBefore(Pin *pin);
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void connectPinAfter(Pin *pin);
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void disconnectPinBefore(Pin *pin);
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void pinSetFuncAfter(Pin *pin);
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protected:
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void ensureConstantFuncPins();
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void recordConstPinFunc(Pin *pin);
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virtual void seedConstants();
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void seedInvalidConstants();
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void propagateConstants();
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void setConstraintConstPins(LogicValueMap *pin_value_map,
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bool propagate);
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void setConstFuncPins(bool propagate);
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void enqueueConstantPinInputs(bool propagate);
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virtual void setPinValue(const Pin *pin,
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LogicValue value,
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bool propagate);
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void enqueue(const Instance *inst);
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void evalInstance(const Instance *inst);
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LogicValue clockGateOutValue(const Instance *inst);
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TimingSense functionSense(const FuncExpr *expr,
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const Pin *input_pin,
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const Instance *inst);
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void functionSense(const FuncExpr *expr,
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const Pin *input_pin,
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const Instance *inst,
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// return values
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TimingSense &sense,
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LogicValue &value) const;
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void clearSimValues();
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virtual void clearInstSimValues(const Instance *inst);
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void annotateGraphEdges();
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void annotateVertexEdges(const Instance *inst,
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const Pin *pin,
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Vertex *vertex,
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bool annotate);
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void annotateVertexEdges(const Instance *inst,
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bool annotate);
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void removePropagatedValue(const Pin *pin);
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void propagateFromInvalidDrvrsToLoads();
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void propagateToInvalidLoads();
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void propagateDrvrToLoad(Pin *drvr_pin,
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Pin *load_pin);
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void setSimValue(Vertex *vertex,
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LogicValue value);
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SimObserver *observer_;
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bool valid_;
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bool incremental_;
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// Cache of pins that have constant functions (tie high and tie low
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// cell instances).
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PinSet const_func_pins_;
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bool const_func_pins_valid_;
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// Instances that require incremental constant propagation.
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InstanceSet invalid_insts_;
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// Driver pins waiting to propagate constant to loads.
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PinSet invalid_drvr_pins_;
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// Load pins that waiting for the driver constant to propagate.
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PinSet invalid_load_pins_;
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EvalQueue eval_queue_;
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// Instances with constant pin values for annotateVertexEdges.
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InstanceSet instances_with_const_pins_;
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InstanceSet instances_to_annotate_;
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#ifdef CUDD
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DdNode *funcBdd(const FuncExpr *expr,
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const Instance *inst) const;
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DdNode *ensureNode(LibertyPort *port) const;
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void clearSymtab() const;
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DdManager *cudd_manager_;
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mutable BddSymbolTable symtab_;
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mutable std::mutex cudd_lock_;
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#endif // CUDD
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private:
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DISALLOW_COPY_AND_ASSIGN(Sim);
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};
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// Abstract base class for Sim value change observer.
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class SimObserver
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{
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public:
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SimObserver() {}
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virtual ~SimObserver() {}
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virtual void valueChangeAfter(Vertex *vertex) = 0;
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virtual void faninEdgesChangeAfter(Vertex *vertex) = 0;
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virtual void fanoutEdgesChangeAfter(Vertex *vertex) = 0;
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private:
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DISALLOW_COPY_AND_ASSIGN(SimObserver);
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};
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bool
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logicValueZeroOne(LogicValue value);
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// Edge cond (liberty "when") function is disabled (evals to zero).
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bool
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isCondDisabled(Edge *edge,
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const Instance *inst,
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const Pin *from_pin,
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const Pin *to_pin,
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const Network *network,
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const Sim *sim);
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// isCondDisabled but also return the cond expression that causes
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// the disable. This can differ from the edge cond expression
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// when the default timing edge is disabled by another edge between
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// the same pins that is enabled.
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void
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isCondDisabled(Edge *edge,
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const Instance *inst,
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const Pin *from_pin,
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const Pin *to_pin,
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const Network *network,
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const Sim *sim,
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bool &is_disabled,
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FuncExpr *&disable_cond);
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// Edge mode function is disabled (evals to zero).
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bool
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isModeDisabled(Edge *edge,
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const Instance *inst,
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const Network *network,
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const Sim *sim);
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void
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isModeDisabled(Edge *edge,
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const Instance *inst,
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const Network *network,
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const Sim *sim,
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bool &is_disabled,
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FuncExpr *&disable_cond);
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// Edge is disabled because by test scan enable.
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// from scan_data_in and scan_enable=1
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// from scan_in and scan_enable=0
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bool
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isTestDisabled(const Instance *inst,
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const Pin *from_pin,
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const Pin *to_pin,
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const Network *network,
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const Sim *sim);
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void
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isTestDisabled(const Instance *inst,
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const Pin *from_pin,
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const Pin *to_pin,
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const Network *network,
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const Sim *sim,
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bool &is_disabled,
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Pin *&scan_enable);
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} // namespace
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