127 lines
3.9 KiB
C++
127 lines
3.9 KiB
C++
// OpenSTA, Static Timing Analyzer
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// Copyright (c) 2019, Parallax Software, Inc.
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//
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <https://www.gnu.org/licenses/>.
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#include "Machine.hh"
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#include "Liberty.hh"
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#include "Network.hh"
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#include "Sdc.hh"
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#include "Parasitics.hh"
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#include "GraphDelayCalc.hh"
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#include "RCDelayCalc.hh"
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namespace sta {
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RCDelayCalc::RCDelayCalc(StaState *sta) :
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LumpedCapDelayCalc(sta)
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{
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}
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ArcDelayCalc *
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RCDelayCalc::copy()
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{
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return new RCDelayCalc(this);
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}
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void
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RCDelayCalc::findParasitic(const Pin *drvr_pin,
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const TransRiseFall *tr,
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const DcalcAnalysisPt *dcalc_ap,
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// Return values.
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Parasitic *¶sitic,
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bool &delete_at_finish)
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{
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parasitic = NULL;
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delete_at_finish = false;
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// set_load has precidence over parasitics.
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if (!sdc_->drvrPinHasWireCap(drvr_pin)) {
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const OperatingConditions *op_cond = dcalc_ap->operatingConditions();
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const Corner *corner = dcalc_ap->corner();
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const MinMax *cnst_min_max = dcalc_ap->constraintMinMax();
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const ParasiticAnalysisPt *parasitic_ap = dcalc_ap->parasiticAnalysisPt();
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// Prefer PiElmore.
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parasitic = parasitics_->findPiElmore(drvr_pin, tr, parasitic_ap);
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if (parasitic == NULL) {
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Parasitic *parasitic_network =
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parasitics_->findParasiticNetwork(drvr_pin, parasitic_ap);
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if (parasitic_network) {
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parasitic = parasitics_->reduceToPiElmore(parasitic_network, drvr_pin,
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tr, op_cond, corner,
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cnst_min_max, parasitic_ap);
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delete_at_finish = true;
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}
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}
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if (parasitic == NULL)
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parasitic = parasitics_->findLumpedElmore(drvr_pin, tr, parasitic_ap);
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if (parasitic == NULL) {
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Wireload *wireload = sdc_->wireloadDefaulted(cnst_min_max);
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if (wireload) {
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float pin_cap, wire_cap, fanout;
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bool has_wire_cap;
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graph_delay_calc_->netCaps(drvr_pin, tr, dcalc_ap,
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pin_cap, wire_cap, fanout, has_wire_cap);
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parasitic = parasitics_->estimatePiElmore(drvr_pin, tr, wireload,
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fanout, pin_cap, op_cond,
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corner, cnst_min_max,
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parasitic_ap);
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delete_at_finish = true;
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}
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}
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}
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}
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void
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RCDelayCalc::inputPortDelay(const Pin *,
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float in_slew,
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const TransRiseFall *tr,
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Parasitic *parasitic,
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const DcalcAnalysisPt *)
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{
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drvr_parasitic_ = parasitic;
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drvr_slew_ = in_slew;
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drvr_tr_ = tr;
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drvr_cell_ = NULL;
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drvr_library_ = network_->defaultLibertyLibrary();
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multi_drvr_slew_factor_ = 1.0F;
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}
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// For DSPF on an input port the elmore delay is used as the time
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// constant of an exponential waveform. The delay to the logic
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// threshold and slew are computed for the exponential waveform.
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// Note that this uses the driver thresholds and relies on
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// thresholdAdjust to convert the delay and slew to the load's thresholds.
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void
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RCDelayCalc::dspfWireDelaySlew(const Pin *,
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float elmore,
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ArcDelay &wire_delay,
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Slew &load_slew)
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{
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float vth = .5;
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float vl = .2;
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float vh = .8;
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float slew_derate = 1.0;
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if (drvr_library_) {
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vth = drvr_library_->inputThreshold(drvr_tr_);
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vl = drvr_library_->slewLowerThreshold(drvr_tr_);
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vh = drvr_library_->slewUpperThreshold(drvr_tr_);
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slew_derate = drvr_library_->slewDerateFromLibrary();
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}
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wire_delay = static_cast<float>(-elmore * log(1.0 - vth));
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load_slew = (drvr_slew_ + elmore * log((1.0 - vl) / (1.0 - vh))
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/ slew_derate) * multi_drvr_slew_factor_;
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}
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} // namespace
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