46 lines
1.5 KiB
Tcl
46 lines
1.5 KiB
Tcl
# OpenSTA, Static Timing Analyzer
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# Copyright (c) 2024, Parallax Software, Inc.
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#
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# This program is free software: you can redistribute it and/or modify
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# it under the terms of the GNU General Public License as published by
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# the Free Software Foundation, either version 3 of the License, or
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# (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program. If not, see <https://www.gnu.org/licenses/>.
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namespace eval sta {
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# Defined by SWIG interface Verilog.i.
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define_cmd_args "read_verilog" {filename}
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proc_redirect read_verilog {
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read_verilog_cmd [file nativename [lindex $args 0]]
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}
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define_cmd_args "write_verilog" {[-sort] [-include_pwr_gnd]\
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[-remove_cells cells] filename}
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proc write_verilog { args } {
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parse_key_args "write_verilog" args keys {-remove_cells} \
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flags {-sort -include_pwr_gnd}
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set remove_cells {}
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if { [info exists keys(-remove_cells)] } {
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set remove_cells [parse_cell_arg $keys(-remove_cells)]
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}
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set sort [info exists flags(-sort)]
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set include_pwr_gnd [info exists flags(-include_pwr_gnd)]
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check_argc_eq1 "write_verilog" $args
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set filename [file nativename [lindex $args 0]]
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write_verilog_cmd $filename $sort $include_pwr_gnd $remove_cells
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}
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# sta namespace end
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}
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