26 lines
387 B
Plaintext
26 lines
387 B
Plaintext
module verilog_test1 (clk,
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in1,
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out1);
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input clk;
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input in1;
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output out1;
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wire n1;
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wire wire_a;
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wire wire_b;
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wire wire_c;
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wire wire_d;
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wire wire_e;
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BUF_X1 buf1 (.A(in1),
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.Z(n1));
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BUF_X4 buf_x4 (.A(wire_e));
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NAND2_X1 nand1 (.A1(wire_a),
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.A2(wire_b));
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NOR2_X1 nor1 (.A1(wire_c),
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.A2(wire_d));
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DFF_X1 reg1 (.D(n1),
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.CK(clk),
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.Q(out1));
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endmodule
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