498 lines
19 KiB
Plaintext
498 lines
19 KiB
Plaintext
--- Master clock properties ---
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clk name: clk
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clk full_name: clk
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clk period: 10.000000
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clk is_generated: 0
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clk is_virtual: 0
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clk is_propagated: 0
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clk sources: 1
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src: clk
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--- Generated clock properties ---
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div_clk name: div_clk
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div_clk full_name: div_clk
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div_clk period: 20.000000
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div_clk is_generated: 1
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div_clk is_virtual: 0
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div_clk is_propagated: 0
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div_clk sources: 1
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src: div_reg/Q
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--- Propagated clock toggle ---
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clk is_propagated (after set): 1
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div_clk is_propagated (after set): 0
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clk is_propagated (after unset): 0
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--- Virtual clock ---
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vclk is_virtual: 1
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vclk is_generated: 0
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vclk period: 5.000000
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vclk sources: 0
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--- Pin clocks/clock_domains ---
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reg1/CK clocks: 1
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reg1/CK clock_domains: 1
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reg2/CK clocks: 1
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reg2/CK clock_domains: 1
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reg1/D clocks: 0
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reg1/Q clocks: 0
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--- GenClk full_clock_expanded max ---
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Startpoint: reg2 (rising edge-triggered flip-flop clocked by div_clk)
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Endpoint: out2 (output port clocked by div_clk)
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Path Group: div_clk
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Path Type: max
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Fanout Cap Slew Delay Time Description
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-----------------------------------------------------------------------------
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0.00 0.00 0.00 clock div_clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 0.00 ^ reg2/CK (DFF_X1)
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1 0.97 0.01 0.08 0.08 ^ reg2/Q (DFF_X1)
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n4 (net)
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0.01 0.00 0.08 ^ buf3/A (BUF_X1)
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1 0.00 0.00 0.02 0.10 ^ buf3/Z (BUF_X1)
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out2 (net)
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0.00 0.00 0.10 ^ out2 (out)
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0.10 data arrival time
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0.00 20.00 20.00 clock div_clk (rise edge)
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0.00 20.00 clock network delay (ideal)
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0.00 20.00 clock reconvergence pessimism
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-1.00 19.00 output external delay
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19.00 data required time
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-----------------------------------------------------------------------------
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19.00 data required time
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-0.10 data arrival time
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-----------------------------------------------------------------------------
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18.90 slack (MET)
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--- GenClk full_clock_expanded min ---
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Startpoint: reg2 (rising edge-triggered flip-flop clocked by div_clk)
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Endpoint: out2 (output port clocked by div_clk)
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Path Group: div_clk
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Path Type: min
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Fanout Cap Slew Delay Time Description
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-----------------------------------------------------------------------------
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0.00 0.00 0.00 clock div_clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 0.00 ^ reg2/CK (DFF_X1)
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1 0.88 0.01 0.08 0.08 v reg2/Q (DFF_X1)
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n4 (net)
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0.01 0.00 0.08 v buf3/A (BUF_X1)
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1 0.00 0.00 0.02 0.10 v buf3/Z (BUF_X1)
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out2 (net)
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0.00 0.00 0.10 v out2 (out)
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0.10 data arrival time
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0.00 0.00 0.00 clock div_clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 clock reconvergence pessimism
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-1.00 -1.00 output external delay
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-1.00 data required time
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-----------------------------------------------------------------------------
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-1.00 data required time
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-0.10 data arrival time
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-----------------------------------------------------------------------------
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1.10 slack (MET)
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--- GenClk full_clock max ---
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Startpoint: reg2 (rising edge-triggered flip-flop clocked by div_clk)
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Endpoint: out2 (output port clocked by div_clk)
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Path Group: div_clk
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Path Type: max
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Fanout Cap Slew Delay Time Description
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-----------------------------------------------------------------------------
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0.00 0.00 0.00 clock div_clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 0.00 ^ reg2/CK (DFF_X1)
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1 0.97 0.01 0.08 0.08 ^ reg2/Q (DFF_X1)
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1 0.00 0.00 0.02 0.10 ^ buf3/Z (BUF_X1)
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0.00 0.00 0.10 ^ out2 (out)
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0.10 data arrival time
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0.00 20.00 20.00 clock div_clk (rise edge)
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0.00 20.00 clock network delay (ideal)
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0.00 20.00 clock reconvergence pessimism
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-1.00 19.00 output external delay
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19.00 data required time
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-----------------------------------------------------------------------------
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19.00 data required time
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-0.10 data arrival time
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-----------------------------------------------------------------------------
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18.90 slack (MET)
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--- GenClk full max ---
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Startpoint: reg2 (rising edge-triggered flip-flop clocked by div_clk)
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Endpoint: out2 (output port clocked by div_clk)
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Path Group: div_clk
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Path Type: max
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Fanout Cap Slew Delay Time Description
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-----------------------------------------------------------------------------
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0.00 0.00 0.00 clock div_clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 0.00 ^ reg2/CK (DFF_X1)
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1 0.97 0.01 0.08 0.08 ^ reg2/Q (DFF_X1)
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1 0.00 0.00 0.02 0.10 ^ buf3/Z (BUF_X1)
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0.00 0.00 0.10 ^ out2 (out)
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0.10 data arrival time
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0.00 20.00 20.00 clock div_clk (rise edge)
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0.00 20.00 clock network delay (ideal)
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0.00 20.00 clock reconvergence pessimism
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-1.00 19.00 output external delay
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19.00 data required time
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-----------------------------------------------------------------------------
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19.00 data required time
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-0.10 data arrival time
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-----------------------------------------------------------------------------
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18.90 slack (MET)
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--- GenClk all formats ---
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Startpoint: reg2 (rising edge-triggered flip-flop clocked by div_clk)
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Endpoint: out2 (output port clocked by div_clk)
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Path Group: div_clk
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Path Type: max
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max_delay/setup group div_clk
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Required Actual
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Endpoint Delay Delay Slack
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------------------------------------------------------------
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out2 (output) 19.00 0.10 18.90 (MET)
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Startpoint Endpoint Slack
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--------------------------------------------------------------------------------
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reg2/Q (search_genclk) out2 (output) 18.90
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Group Slack
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--------------------------------------------
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div_clk 18.90
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{"checks": [
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{
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"type": "output_delay",
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"path_group": "div_clk",
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"path_type": "max",
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"startpoint": "reg2/Q",
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"endpoint": "out2",
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"source_clock": "div_clk",
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"source_clock_edge": "rise",
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"source_clock_path": [
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{
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"instance": "div_reg",
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"cell": "DFF_X1",
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"verilog_src": "",
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"pin": "div_reg/Q",
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"net": "div_clk",
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"arrival": 0.000e+00,
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"capacitance": 9.497e-16,
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"slew": 7.270e-12
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},
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{
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"instance": "reg2",
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"cell": "DFF_X1",
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"verilog_src": "",
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"pin": "reg2/CK",
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"net": "div_clk",
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"arrival": 0.000e+00,
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"slew": 7.270e-12
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}
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],
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"source_path": [
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{
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"instance": "reg2",
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"cell": "DFF_X1",
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"verilog_src": "",
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"pin": "reg2/Q",
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"net": "n4",
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"arrival": 8.371e-11,
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"capacitance": 9.747e-16,
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"slew": 7.314e-12
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},
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{
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"instance": "buf3",
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"cell": "BUF_X1",
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"verilog_src": "",
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"pin": "buf3/A",
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"net": "n4",
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"arrival": 8.371e-11,
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"slew": 7.314e-12
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},
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{
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"instance": "buf3",
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"cell": "BUF_X1",
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"verilog_src": "",
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"pin": "buf3/Z",
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"net": "out2",
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"arrival": 1.003e-10,
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"capacitance": 0.000e+00,
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"slew": 3.638e-12
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},
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{
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"instance": "",
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"cell": "search_genclk",
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"verilog_src": "",
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"pin": "out2",
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"arrival": 1.003e-10,
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"slew": 3.638e-12
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}
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],
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"target_clock": "div_clk",
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"target_clock_edge": "rise",
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"data_arrival_time": 1.003e-10,
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"crpr": 0.000e+00,
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"margin": 1.000e-09,
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"required_time": 1.900e-08,
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"slack": 1.890e-08
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}
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]
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}
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--- GenClk propagated full_clock_expanded ---
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Startpoint: reg2 (rising edge-triggered flip-flop clocked by div_clk)
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Endpoint: out2 (output port clocked by div_clk)
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Path Group: div_clk
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Path Type: max
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Fanout Cap Slew Delay Time Description
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-----------------------------------------------------------------------------
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0.00 0.00 0.00 clock div_clk (rise edge)
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0.00 0.00 clock source latency
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1 0.78 0.00 0.00 0.00 ^ clk (in)
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0.00 0.00 0.00 ^ clkbuf/A (CLKBUF_X1)
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2 1.90 0.01 0.03 0.03 ^ clkbuf/Z (CLKBUF_X1)
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0.01 0.00 0.03 ^ div_reg/CK (DFF_X1)
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1 0.95 0.01 0.09 0.11 ^ div_reg/Q (DFF_X1)
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0.00 0.11 clock network delay (ideal)
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0.00 0.00 0.11 ^ reg2/CK (DFF_X1)
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1 0.97 0.01 0.08 0.20 ^ reg2/Q (DFF_X1)
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0.01 0.00 0.20 ^ buf3/A (BUF_X1)
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1 0.00 0.00 0.02 0.21 ^ buf3/Z (BUF_X1)
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0.00 0.00 0.21 ^ out2 (out)
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0.21 data arrival time
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0.00 20.00 20.00 clock div_clk (rise edge)
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0.11 20.11 clock network delay (ideal)
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0.00 20.11 clock reconvergence pessimism
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-1.00 19.11 output external delay
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19.11 data required time
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-----------------------------------------------------------------------------
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19.11 data required time
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-0.21 data arrival time
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-----------------------------------------------------------------------------
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18.90 slack (MET)
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Startpoint: reg2 (rising edge-triggered flip-flop clocked by div_clk)
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Endpoint: out2 (output port clocked by div_clk)
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Path Group: div_clk
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Path Type: min
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Fanout Cap Slew Delay Time Description
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-----------------------------------------------------------------------------
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0.00 0.00 0.00 clock div_clk (rise edge)
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0.00 0.00 clock source latency
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1 0.78 0.00 0.00 0.00 ^ clk (in)
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0.00 0.00 0.00 ^ clkbuf/A (CLKBUF_X1)
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2 1.90 0.01 0.03 0.03 ^ clkbuf/Z (CLKBUF_X1)
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0.01 0.00 0.03 ^ div_reg/CK (DFF_X1)
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1 0.95 0.01 0.09 0.11 ^ div_reg/Q (DFF_X1)
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0.00 0.11 clock network delay (ideal)
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0.00 0.00 0.11 ^ reg2/CK (DFF_X1)
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1 0.88 0.01 0.08 0.19 v reg2/Q (DFF_X1)
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0.01 0.00 0.19 v buf3/A (BUF_X1)
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1 0.00 0.00 0.02 0.21 v buf3/Z (BUF_X1)
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0.00 0.00 0.21 v out2 (out)
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0.21 data arrival time
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0.00 0.00 0.00 clock div_clk (rise edge)
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0.11 0.11 clock network delay (ideal)
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0.00 0.11 clock reconvergence pessimism
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-1.00 -0.89 output external delay
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-0.89 data required time
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-----------------------------------------------------------------------------
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-0.89 data required time
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-0.21 data arrival time
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-----------------------------------------------------------------------------
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1.10 slack (MET)
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--- find_timing_paths genclk domain ---
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Warning 502: search_genclk_property_report.tcl line 1, find_timing_paths -endpoint_count is deprecated. Use -endpoint_path_count instead.
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GenClk max paths: 2
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pin=out2 slack=1.889971379398503e-8
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is_check: 0 is_output: 1
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target_clk: div_clk
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startpoint_clock: div_clk
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endpoint_clock: div_clk
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points: 4
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pin=out2 slack=1.890143330740557e-8
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is_check: 0 is_output: 1
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target_clk: div_clk
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startpoint_clock: div_clk
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endpoint_clock: div_clk
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points: 4
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--- report_path_cmd genclk ---
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Fanout Cap Slew Delay Time Description
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-----------------------------------------------------------------------------
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0.00 0.00 0.00 clock div_clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 0.00 ^ reg2/CK (DFF_X1)
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1 0.97 0.01 0.08 0.08 ^ reg2/Q (DFF_X1)
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0.01 0.00 0.08 ^ buf3/A (BUF_X1)
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1 0.00 0.00 0.02 0.10 ^ buf3/Z (BUF_X1)
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0.00 0.00 0.10 ^ out2 (out)
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--- report_path_ends genclk ---
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Startpoint: reg2 (rising edge-triggered flip-flop clocked by div_clk)
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Endpoint: out2 (output port clocked by div_clk)
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Path Group: div_clk
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Path Type: max
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Fanout Cap Slew Delay Time Description
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-----------------------------------------------------------------------------
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0.00 0.00 0.00 clock div_clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 0.00 ^ reg2/CK (DFF_X1)
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1 0.97 0.01 0.08 0.08 ^ reg2/Q (DFF_X1)
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0.01 0.00 0.08 ^ buf3/A (BUF_X1)
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1 0.00 0.00 0.02 0.10 ^ buf3/Z (BUF_X1)
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0.00 0.00 0.10 ^ out2 (out)
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0.10 data arrival time
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0.00 20.00 20.00 clock div_clk (rise edge)
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0.00 20.00 clock network delay (ideal)
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0.00 20.00 clock reconvergence pessimism
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-1.00 19.00 output external delay
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19.00 data required time
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-----------------------------------------------------------------------------
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19.00 data required time
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-0.10 data arrival time
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-----------------------------------------------------------------------------
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18.90 slack (MET)
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Startpoint: reg2 (rising edge-triggered flip-flop clocked by div_clk)
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Endpoint: out2 (output port clocked by div_clk)
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Path Group: div_clk
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Path Type: max
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Fanout Cap Slew Delay Time Description
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-----------------------------------------------------------------------------
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0.00 0.00 0.00 clock div_clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 0.00 ^ reg2/CK (DFF_X1)
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1 0.88 0.01 0.08 0.08 v reg2/Q (DFF_X1)
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0.01 0.00 0.08 v buf3/A (BUF_X1)
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1 0.00 0.00 0.02 0.10 v buf3/Z (BUF_X1)
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0.00 0.00 0.10 v out2 (out)
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0.10 data arrival time
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0.00 20.00 20.00 clock div_clk (rise edge)
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0.00 20.00 clock network delay (ideal)
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0.00 20.00 clock reconvergence pessimism
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-1.00 19.00 output external delay
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19.00 data required time
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-----------------------------------------------------------------------------
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19.00 data required time
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-0.10 data arrival time
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-----------------------------------------------------------------------------
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18.90 slack (MET)
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--- report_clock_properties ---
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Clock Period Waveform
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----------------------------------------------------
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clk 10.00 0.00 5.00
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div_clk 20.00 0.00 10.00 (generated)
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vclk 5.00 0.00 2.50
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--- report_clock_skew ---
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Clock clk
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0.03 source latency div_reg/CK ^
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-0.03 target latency div_reg/CK ^
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0.00 CRPR
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--------------
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0.00 setup skew
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Clock div_clk
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No launch/capture paths found.
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Clock vclk
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No launch/capture paths found.
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Clock clk
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0.03 source latency div_reg/CK ^
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-0.03 target latency div_reg/CK ^
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0.00 CRPR
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--------------
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0.00 hold skew
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Clock div_clk
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No launch/capture paths found.
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Clock vclk
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No launch/capture paths found.
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--- GenClk digits ---
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Startpoint: reg2 (rising edge-triggered flip-flop clocked by div_clk)
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Endpoint: out2 (output port clocked by div_clk)
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Path Group: div_clk
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Path Type: max
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Delay Time Description
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-----------------------------------------------------------------
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0.000000 0.000000 clock div_clk (rise edge)
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0.000000 0.000000 clock network delay (ideal)
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0.000000 0.000000 ^ reg2/CK (DFF_X1)
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0.083707 0.083707 ^ reg2/Q (DFF_X1)
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0.016579 0.100286 ^ buf3/Z (BUF_X1)
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0.000000 0.100286 ^ out2 (out)
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0.100286 data arrival time
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20.000000 20.000000 clock div_clk (rise edge)
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0.000000 20.000000 clock network delay (ideal)
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0.000000 20.000000 clock reconvergence pessimism
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-1.000000 19.000000 output external delay
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19.000000 data required time
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-----------------------------------------------------------------
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19.000000 data required time
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-0.100286 data arrival time
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-----------------------------------------------------------------
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18.899714 slack (MET)
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Startpoint: reg2 (rising edge-triggered flip-flop clocked by div_clk)
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Endpoint: out2 (output port clocked by div_clk)
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Path Group: div_clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock div_clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 ^ reg2/CK (DFF_X1)
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0.08 0.08 ^ reg2/Q (DFF_X1)
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0.02 0.10 ^ buf3/Z (BUF_X1)
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0.00 0.10 ^ out2 (out)
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0.10 data arrival time
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20.00 20.00 clock div_clk (rise edge)
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0.00 20.00 clock network delay (ideal)
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0.00 20.00 clock reconvergence pessimism
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-1.00 19.00 output external delay
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19.00 data required time
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---------------------------------------------------------
|
|
19.00 data required time
|
|
-0.10 data arrival time
|
|
---------------------------------------------------------
|
|
18.90 slack (MET)
|
|
|
|
|
|
--- tns/wns ---
|
|
tns max 0.00
|
|
wns max 0.00
|
|
worst slack max 7.90
|
|
worst slack min 0.05
|