85 lines
3.0 KiB
Verilog
85 lines
3.0 KiB
Verilog
// Verilog design exercising error-adjacent paths in VerilogReader.cc:
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// - Bus expressions with partial bit ranges
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// - Assign statements with concatenation
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// - Module instances with varied port connection styles
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// - Named and positional port connections
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// - Escaped identifiers
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module sub_mod (input A, input B, output Y);
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wire n1;
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AND2_X1 and_inner (.A1(A), .A2(B), .ZN(n1));
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BUF_X1 buf_inner (.A(n1), .Z(Y));
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endmodule
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module verilog_error_paths (clk, din, dout, sel, en,
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bus_in, bus_out, flag);
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input clk;
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input [3:0] din;
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output [3:0] dout;
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input sel, en;
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input [7:0] bus_in;
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output [7:0] bus_out;
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output flag;
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wire [3:0] stage1;
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wire [3:0] stage2;
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wire [7:0] wide1;
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wire [7:0] wide2;
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wire w1, w2, w3;
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// Assign with concatenation of bus bits
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assign {stage1[3], stage1[2], stage1[1], stage1[0]} = din;
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// Simple assigns
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assign w1 = sel;
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assign flag = w3;
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// Buffer chain on low bits
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BUF_X1 buf0 (.A(stage1[0]), .Z(stage2[0]));
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BUF_X1 buf1 (.A(stage1[1]), .Z(stage2[1]));
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BUF_X2 buf2 (.A(stage1[2]), .Z(stage2[2]));
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BUF_X2 buf3 (.A(stage1[3]), .Z(stage2[3]));
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// AND gate with enable
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AND2_X1 and_en (.A1(stage2[0]), .A2(en), .ZN(w2));
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// OR gate
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OR2_X1 or_sel (.A1(w2), .A2(w1), .ZN(w3));
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// Sub-module instantiation (hierarchical)
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sub_mod sub1 (.A(stage2[1]), .B(stage2[2]), .Y(wide1[0]));
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sub_mod sub2 (.A(stage2[2]), .B(stage2[3]), .Y(wide1[1]));
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// Direct wiring for remaining bus bits
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BUF_X1 buf_w2 (.A(stage2[0]), .Z(wide1[2]));
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BUF_X1 buf_w3 (.A(stage2[1]), .Z(wide1[3]));
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BUF_X1 buf_w4 (.A(stage2[2]), .Z(wide1[4]));
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BUF_X1 buf_w5 (.A(stage2[3]), .Z(wide1[5]));
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INV_X1 inv_w6 (.A(stage2[0]), .ZN(wide1[6]));
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INV_X1 inv_w7 (.A(stage2[1]), .ZN(wide1[7]));
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// Wide bus through more gates
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AND2_X1 and_b0 (.A1(bus_in[0]), .A2(wide1[0]), .ZN(wide2[0]));
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AND2_X1 and_b1 (.A1(bus_in[1]), .A2(wide1[1]), .ZN(wide2[1]));
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AND2_X1 and_b2 (.A1(bus_in[2]), .A2(wide1[2]), .ZN(wide2[2]));
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AND2_X1 and_b3 (.A1(bus_in[3]), .A2(wide1[3]), .ZN(wide2[3]));
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OR2_X1 or_b4 (.A1(bus_in[4]), .A2(wide1[4]), .ZN(wide2[4]));
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OR2_X1 or_b5 (.A1(bus_in[5]), .A2(wide1[5]), .ZN(wide2[5]));
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OR2_X1 or_b6 (.A1(bus_in[6]), .A2(wide1[6]), .ZN(wide2[6]));
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OR2_X1 or_b7 (.A1(bus_in[7]), .A2(wide1[7]), .ZN(wide2[7]));
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// Output registers
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DFF_X1 reg0 (.D(stage2[0]), .CK(clk), .Q(dout[0]));
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DFF_X1 reg1 (.D(stage2[1]), .CK(clk), .Q(dout[1]));
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DFF_X1 reg2 (.D(stage2[2]), .CK(clk), .Q(dout[2]));
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DFF_X1 reg3 (.D(stage2[3]), .CK(clk), .Q(dout[3]));
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DFF_X1 reg_b0 (.D(wide2[0]), .CK(clk), .Q(bus_out[0]));
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DFF_X1 reg_b1 (.D(wide2[1]), .CK(clk), .Q(bus_out[1]));
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DFF_X1 reg_b2 (.D(wide2[2]), .CK(clk), .Q(bus_out[2]));
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DFF_X1 reg_b3 (.D(wide2[3]), .CK(clk), .Q(bus_out[3]));
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DFF_X1 reg_b4 (.D(wide2[4]), .CK(clk), .Q(bus_out[4]));
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DFF_X1 reg_b5 (.D(wide2[5]), .CK(clk), .Q(bus_out[5]));
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DFF_X1 reg_b6 (.D(wide2[6]), .CK(clk), .Q(bus_out[6]));
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DFF_X1 reg_b7 (.D(wide2[7]), .CK(clk), .Q(bus_out[7]));
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endmodule
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