OpenSTA/verilog
Jaehyun Kim a22112fe8f Merge remote-tracking branch 'origin/master' into secure-sta-test-by-opus
# Conflicts:
#	verilog/test/CMakeLists.txt

Signed-off-by: Jaehyun Kim <jhkim@precisioninno.com>
2026-04-02 12:30:18 +09:00
..
test Merge remote-tracking branch 'origin/master' into secure-sta-test-by-opus 2026-04-02 12:30:18 +09:00
Verilog.i update copyright 2026-03-10 14:57:45 -07:00
Verilog.tcl update copyright 2026-03-10 14:57:45 -07:00
VerilogLex.ll string squash 2026-03-28 19:13:35 -07:00
VerilogParse.yy string squash 2026-03-28 19:13:35 -07:00
VerilogReader.cc string squash 2026-03-28 19:13:35 -07:00
VerilogReaderPvt.hh string squash 2026-03-28 19:13:35 -07:00
VerilogScanner.hh string squash 2026-03-28 19:13:35 -07:00
VerilogWriter.cc fix to exclude bias pins from timing graph 2026-04-02 00:56:38 +00:00