24 lines
740 B
Tcl
24 lines
740 B
Tcl
read_liberty liberty_arcs_one2one.lib
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puts "TEST 1:"
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read_verilog liberty_arcs_one2one_1.v
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link_design liberty_arcs_one2one_1
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create_clock -name clk -period 0
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set_input_delay -clock clk 0 [all_inputs]
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set_output_delay -clock clk 0 [all_outputs]
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for {set i 0} {$i < 8} {incr i} {
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puts "report_edges -from partial_wide_inv_cell/A[$i]"
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report_edges -from partial_wide_inv_cell/A[$i]
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}
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puts "TEST 2:"
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read_verilog liberty_arcs_one2one_2.v
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link_design liberty_arcs_one2one_2
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create_clock -name clk -period 0
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set_input_delay -clock clk 0 [all_inputs]
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set_output_delay -clock clk 0 [all_outputs]
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for {set i 0} {$i < 8} {incr i} {
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puts "report_edges -to partial_wide_inv_cell/Y[$i]"
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report_edges -to partial_wide_inv_cell/Y[$i]
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}
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